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ISL5239KI 데이터시트(PDF) 10 Page - Intersil Corporation |
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ISL5239KI 데이터시트(HTML) 10 Page - Intersil Corporation |
10 / 31 page 10 cross-coupled term on both the I and Q channels. Typical implementation is as shown in Figure 10. The Output formatter also provides DC offset correction to 1/4 LSB for 18-bit outputs to reduce analog DC offsets introduced in external D/A conversion and modulation circuits which can degrade system performance by causing carrier feed through in complex baseband systems, or spurs at DC for IF systems. The ODC also provides programmable output precision 8 to 18-bits, with unbiased (convergent) rounding, since practical system designs will require D/A converters with fewer than 18-bits. Internal accuracy is in excess of 18-bits, and utilizes 20-bit data paths in critical areas. Additionally, both two’s complement and offset binary formats are supported. Capture Memory (CM) The Capture Memory allows the capture and viewing of data from various points in the chip. The primary function is to capture the digital signals coming into the pre-distorter. The CM also provides a secondary mode, as it can provide stimulus directly to the pre-Distorter. The CM is comprised of both the Input and the Feedback Memories. The processor interface provides the access to view, input, and alter the memory data. Synchronized (triggered) capture of both input and feedback signals is a typical requirement of adaptive digital pre-distortion systems. Input Memory The input capture memory observes the signals going into the amplifier. The 2K deep memory grabs complex samples of data at one of three possible locations, either at the input to the pre-distorter, the output of the pre-distorter, or from its magnitude calculation. In addition to capturing input data, this memory may also be configured as a data source. The input capture memory may be pre-loaded with user defined data and ‘played’ into the pre-distorter to stimulate the system with signals that will elicit a desired response. Feedback Memory The feedback memory allows the user to capture data from an external system and to view the memory through the processor interface. The feedback memory is used to observe the signals coming out of the amplifier. The 1K deep memory grabs 20-bit data, either in parallel or serial format. The feedback capture memory has its own clock input, FBCLK, which must be synchronously derived from CLK and meet the timing requirements. Capture operations may be triggered by an external signal (TRIGIN), by magnitude threshold crossings detection programmed in the magnitude threshold maximum and minimum values, or by system software writing to the processor trigger bit in control word 0x04, bit 6. Separate programmable delays of up to 32k samples are provided for both input memory and feedback capture, allowing system delays to be calibrated out for optimum alignment prior to analysis. A TRIGOUT output is provided to indicates when a capture operation has begun. The processor interface to the capture memories is designed to minimize the time required for loading/unloading. Although access to the memories takes place through indirect address and data registers, auto incrementing of the address is supported so the address only needs to be written once to access the entire memory. The capture memory is as shown in Figure 13. Memory Modes and Programming Instructions Unless noted, the following discussion applies to both the input memory and feedback memory operations. Prior to invoking the memory to capture or send data, the control word 0x06, bits 14:0 input trigger delay counter, 0x08 bits 14:0 feedback trigger delay count, 0x05, bits 10:0 input length, 0x04, bits 2:1 input memory datain source or 0x04, bit 8 feedback input format, and 0x04, bits 5:4 trigger select registers must be loaded. FIGURE 11. IMBALANCE CORRECTION FIGURE 12. CAPTURE MEMORY BLOCK DIAGRAM MEMORY SELECT FB DELAY COUNT uP INTERFACE INPUT ADDR DATA CAPTURE MEMORY 2K FEEDBACK CAPTURE MEMORY 1K FORMAT FB<19:0> FBCLK uP FB STATE TRIG DATA ADDR INPUT uP INPUT SEL STATE IFC I,Q PD I,Q PD MAG TRIGIN MAG COMP uP TRIG SEL INPUT DELAY COUNT CM TEST I,Q ISL5239 |
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