전자부품 데이터시트 검색엔진 |
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ISL5961IB 데이터시트(PDF) 11 Page - Intersil Corporation |
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ISL5961IB 데이터시트(HTML) 11 Page - Intersil Corporation |
11 / 13 page 11 Propagation Delay The converter requires two clock rising edges for data to be represented at the output. Each rising edge of the clock captures the present data word and outputs the previous data. The propagation delay is therefore 1/CLK, plus <2ns of processing. See Figure 15. Test Service Intersil offers customer-specific testing of CommLink converters with a service called Testdrive. To submit a request, fill out the Testdrive form. The form can be found by doing an ‘entire site search’ at www.intersil.com on the words ‘DAC Testdrive’. Or, send a request to the technical support center. PIN 21 PIN 22 RDIFF ISL5961 RLOAD FIGURE 13. OUTPUT LOADING FOR DATASHEET MEASUREMENTS IOUTB IOUTA VOUT = (2 x IOUTA x REQ)V LOAD SEEN BY THE TRANSFORMER RLOAD REPRESENTS THE 1:1 REQ = 0.5 x (RLOAD // RDIFF) AT EACH OUTPUT FIGURE 14. ALTERNATIVE OUTPUT LOADING PIN 21 PIN 22 ISL5961 IOUTB IOUTA VOUT = (2 x IOUTA x REQ)V REQ = 0.5 x (RLOAD // RDIFF// RA), WHERE RA=RB AT EACH OUTPUT RLOAD RDIFF RA RB LOAD SEEN BY THE TRANSFORMER RLOAD REPRESENTS THE Timing Diagram FIGURE 15. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM CLK IOUT 50% tPW1 tPW2 tSU tHLD tSU tSU tPD tHLD tHLD D13-D0 W0 W1 W2 W3 OUTPUT=W0 OUTPUT=W1 tPD OUTPUT=W-1 ISL5961 |
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