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PD16708 데이터시트(PDF) 11 Page - Renesas Technology Corp

부품명 PD16708
상세설명  300-OUTPUT TFT-LCD GATE DRIVER
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제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

PD16708 데이터시트(HTML) 11 Page - Renesas Technology Corp

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Preliminary Product Information S16071EJ6V0PM
9
µµµµ PD16708
3. PIN FUNCTIONS
Pin Symbol
Pin Name
Pad No.
I/O
Description
O1 to O300
Driver output
162 to 461
Output These pins output scan signals that drive the vertical direction (gate lines) of
a TFT-LCD. The output signals change in synchronization with the rising
edge of shift clock (CLK). The driver output amplitude is VDD2 to VEE.
O0, O301
LCD panel
auxiliary
161, 462
Output Regardless of shift data, these pins output VEE level.
R,/L
Shift direction
control
17, 18, 142, 143
Input
The shift direction control pin of shift register. The shift directions of the shift
registers are as follows.
R,/L = H (right shift) : STVR
→ O1 → O300 → STVL
R,/L = L (left shift) : STVL
→ O300 → O1 → STVR
STVR,
STVL
Start pulse
23, 24, 136, 137
I/O
These refer to the input pins of the internal shift register. The start pulse is
read at the rising edge of CLK, and scan signals are output from the driver
output pins. The input level is VDD1 to VSS (logic level).
CLK
Shift clock
21, 22, 138, 139
Input
This pin inputs a shift clock to the internal shift register.
The shift operation is performed in synchronization with the rising edge of
this input.
/OE
Output enable 9, 10, 150, 151
Input
When these pins go low level, the driver output is fixed to VEE level.
The shift registers are not cleared. Refer to 4. TIMING CHART for details.
/AO
All-on control
11, 12, 148, 149
Input
When these pins go low level, all outputs are fixed to VDD2. These pins are
pulled up to the VDD1 power supply inside the IC.
DUMMY
Dummy
25 to 135, 160, 463
No dummy pins are connected with other pins inside the IC.
PASS
Pass line
1, 2, 158, 159
Connected together internal.
VDD1
Logic power
supply
15, 16, 144, 145
2.3 to 3.6 V
VDD2
Driver positive
power supply
13, 14, 146, 147
10 to 30 V
The driver output: High level
VSS
Logic ground
19, 20, 140, 141
Connect this pin to the ground of the system.
VEE
Negative
power supply
for internal
operation and
driver
3 to 8, 152 to 157
−10 to −3.0 V
Cautions 1. To prevent latch up, turn on power to VDD1, VEE, VDD2 and logic input in this order. Turn off power
in the reverse order. These power up/down sequences must be observed also during transition
period.
2. Insert a capacitor of about 0.1
µµµµF between each power line, as shown below, to secure noise
margin such as VIH and VIL.
VDD2
VDD1
0.1
F
VSS
VEE
µ
0.1
F
µ
0.1
F
µ


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