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PD160088 데이터시트(PDF) 6 Page - Renesas Technology Corp

부품명 PD160088
상세설명  480-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 256-GRAY SCALES)
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제조업체  RENESAS [Renesas Technology Corp]
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Data Sheet S16771EJ1V0DS
4
µPD160088
3.
PIN FUNCTIONS
(1/2)
Pin Symbol
Pin Name
I/O
Description
S1 to S480
Driver
Output
The D/A converted 256-gray-scale analog voltage is output.
D00P to D03P,
D00N to D03N
D10P to D13P,
D10N to D13N
D20P to D23P,
D20N to D23N
Display data
(RSDS)
Input
The display data is input with a width of 12 bits by double edge, viz., the gray
scale data (8 bits) by 3 dots (1 pixel).
R,/L
(CMOS)
Shift direction
control
Input
These refer to the start pulse input/output pins when driver ICs are connected in
cascade.
The shift directions of the shift registers are as follows.
R,/L = H (VDD1 level): STHR input, S1
→ S480, STHL output
R,/L = L (VSS1 level): STHL input, S480
→ S1, STHR output
STHR
(CMOS)
Right shift start
pulse
I/O
R,/L = H (VDD1 level): Becomes the start pulse input pin.
R,/L = L (VSS1 level): Becomes the start pulse output pin.
STHL
(CMOS)
Left shift start
pulse
I/O
R,/L = H (VDD1 level): Becomes the start pulse output pin.
R,/L = L (VSS1 level): Becomes the start pulse input pin.
CLKP, CLKN
(RSDS)
Shift clock
Input
Refers to the shift register’s shift clock input.
The display data is incorporated
into the data register at both of rising and falling edge.
At the falling edge of the 160th clock after the start pulse input, the start pulse
output reaches the high level, thus becoming the start pulse of the next-level
driver.
STB
(CMOS)
Latch
Input
The contents of the data register are transferred to the latch circuit at the rising
edge.
And the output timing and charge sharing function are controlled by
MODE.
Please refer to 9.
RELATIONSHIP BETWEEN MODE, STB, POL
AND OUTPUTWAVEFORM for more detail.
It is necessary to ensure input of
one pulse per horizontal period.
POL
(CMOS)
Polarity
Input
POL = H (VDD1 level): The S2n–1 output uses V0-V8 as the reference supply.
The
S2n output uses V9-V17 as the reference supply.
POL = L (VSS1 level): The S2n–1 output uses V9-V17 as the reference supply.
The
S2n output uses V0-V8 as the reference supply.
S2n-1 indicates the odd output and S2n indicates the even output.
Input of the
POL signal is allowed the setup time (tPOL-STB) with respect to STB’s rising edge.
INV
(CMOS)
Data inversion
Input
Data inversion can invert when display data is loaded.
INV = H (VDD1 level): Data inversion loads display data after inverting it.
INV = L (VSS1 level): Data inversion does NOT INVERT input data.
Please input DC signal. Refer to 6. DATA INVERSION.
LPC
(CMOS)
Low Power Control
LPC = L or Open : Normal mode (default)
LPC = H
: Low power mode (30% lower than normal mode)
This pin is pulled down to the VSS1D inside the IC.
MODE
(CMOS)
Charge Sharing
Control
This pin control the Charge Sharing Function.
MODE = H or Open : Disable
MODE = L
: Enable
But Charge Sharing function works only when POL signal is changed from
previous line. This pin is pulled up to VDD1D inside the IC.
RPI1, RPI2
Line-repair AMP.
Input
RPO1, RPO2
Line-repair AMP.
Output
The driver-ability of the line-repair amp is around twice of the normal analog
output; S1 to S480.
And these outputs are changed at the rising edge of STB and
don’t have a Hi-Z period.
RPI1 (RPI2)
→ impedance changed → RPO1 (RPO2)
Remark
Hi-Z: High impedance


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