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LF48908QC31 데이터시트(PDF) 6 Page - LOGIC Devices Incorporated |
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LF48908QC31 데이터시트(HTML) 6 Page - LOGIC Devices Incorporated |
6 / 16 page DEVICES INCORPORATED LF48908 Two Dimensional Convolver 6 Video Imaging Products 08/9/2000–LDS.48908-J loaded is determined by the data on A2-0 during the load operation. If CREG0 is to be loaded, “010” must be placed on A2-0 during the load opera- tion. If CREG1 is to be loaded, “011” must be placed on A2-0. If desired, the Coefficient Register that is not being used to send data to the multiplier array can be loaded with coefficient data while the LF48908 is in active operation. Address Decoder The Address Decoder is used to load the Control Logic Registers and to determine which Coefficient Register sends data to the multiplier array. To load a Control Logic Register, the address of the register must be placed on A2-0, the data to be written must be placed on the CIN bus, and CS and LD must be asserted. The data is TABLE 2. ALU LOGICAL AND ARITHMETIC OPERATIONS TABLE 1. ALU SHIFT OPERATIONS ALU MICROCODE REGISTER REGISTER BIT 9 8 7 OPERATION 0 0 0 No Shift (Default) 0 0 1 Shift Right 1 0 1 0 Shift Right 2 0 1 1 Shift Right 3 1 0 0 Shift Left 1 1 0 1 Shift Left 2 1 1 0 Shift Left 3 1 1 1 Not Valid Register can hold nine 8-bit values. This allows two different 3 x 3 filter kernels to be stored simultaneously on the LF48908. The outputs of CREG0 and CREG1 are connected to the coefficient inputs of the multiplier array (A through I). The register used to supply the coefficient data is determined by the address written to the Address Decoder. If a “101” is written to the Address Decoder, CREG0 will provide the coefficient data. If a “110” is written to the Address Decoder, CREG1 will be used. It is possible to switch between the two Coefficient Registers in real time. This facilitates adaptive filtering operations. It is important to remem- ber to meet the tLCS timing specifica- tion when switching the Coefficient Registers. When a Coefficient Register is selected to supply data to the multiplier array (one of the registers is always selected), all of its outputs are enabled simultaneously. When RESET is asserted, CREG0 is the default register selected to supply the coeffi- cient data. CREG0 and CREG1 are loaded through CIN7-0 using the A2-0, CS, and LD controls. The nine coefficient values are presented on CIN7-0 one by one, in order from A to I. As each value is placed on CIN7-0, it is latched into the selected Coefficient Register using CS and LD. The register to be latched into the addressed register when LD goes HIGH. To select a Coefficient Register (CREG0 or CREG1) to send data to the multiplier array, the appropriate address must be placed on A2-0, and CS and LD must be asserted. When LD goes HIGH, the addressed register will begin supply- ing coefficient data to the multiplier array. Table 4 lists all of the register addresses. The Control Logic Registers can be modified during active operation of the LF48908. If this is done, it is very important to meet the tLCS timing specification. This is to ensure that the outputs of the Control Logic Registers have enough time to change before the next rising edge of CLK. If tLCS is not met, unexpected results may occur on DOUT19-0 for one clock cycle. There are two situations in which tLCS may ALU MICROCODE REGISTER REGISTER BIT 6 5 4 3 2 1 0 OPERATION 0 0 0 0 0 0 0 Logical (00000000) 1 1 1 1 0 0 0 Logical (11111111) 0 0 1 1 0 0 0 Logical (A) (Default) 0 1 0 1 0 0 0 Logical (B) 1 1 0 0 0 0 0 Logical (A) 1 0 1 0 0 0 0 Logical (B) 0 1 1 0 0 0 1 Arithmetic (A + B) 1 0 0 1 0 1 0 Arithmetic (A – B) 1 0 0 1 1 0 0 Arithmetic (B – A) 0 0 0 1 0 0 0 Logical (A AND B) 0 0 1 0 0 0 0 Logical (A AND B) 0 1 0 0 0 0 0 Logical (A AND B) 0 1 1 1 0 0 0 Logical (A OR B) 1 0 1 1 0 0 0 Logical (A OR B) 1 1 0 1 0 0 0 Logical (A OR B) 1 1 1 0 0 0 0 Logical (A NAND B) 1 0 0 0 0 0 0 Logical (A NOR B) 0 1 1 0 0 0 0 Logical (A XOR B) 1 0 0 1 0 0 0 Logical (A XNOR B) |
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