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8V79S674 데이터시트(PDF) 7 Page - Integrated Device Technology

부품명 8V79S674
상세설명  Clock signal division and distribution
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제조업체  IDT [Integrated Device Technology]
홈페이지  http://www.idt.com
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8V79S674 DATA SHEET
REVISION 2 04/10/15
7
DIFFERENTIAL-TO-3.3V, 2.5V LVPECL
CLOCK DIVIDER AND FANOUT BUFFER
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements have
issues relating to the limitations of the measurement equipment. The
noise floor of the equipment can be higher or lower than the noise
floor of the device. Additive phase noise is dependent on both the
noise floor of the input source and measurement equipment.
The additive phase jitter for this device was measured using a 156.25
MHz Wenzel oscillator as input clock source and an Agilent E5052
Phase noise analyzer.
Offset from Carrier Frequency (Hz)


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