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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STC5415 데이터시트(PDF) 9 Page - Connor-Winfield Corporation |
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STC5415 데이터시트(HTML) 9 Page - Connor-Winfield Corporation |
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9 / 48 page  Page 9 of 48 TM120 Rev:P1.3 Date: September 20, 2011 © Copyright the Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice STC5415 Line Card Clock Data sheet Preliminary 0x36 REF_Priority_Table 19-0 R/W REF1 ~ REF5 priority table 0x37 0x38 0x3C PLL_Status 7-0 R/W PLL status: SYNC, LOS, LOL, OOP, SAP, FEE, DHT, HHA 0x3E PLL_Event_Out 7-0 R/W PLL event out (TBD) 0x3F PLL_Event_In 7-0 R/W PLL event in: Relock 0x40 EX_SYNC_Edge_Config 0-0 R/W Select framing edge (falling or rising edge) for EX_SYNC 0x42 REF1/2_Frame_Phase_Align 7-0 R/W Select framing reference input and sampling edge on selected REF1 and REF2 for frame alignment 0x43 REF3_Frame_Phase_Align 3-0 R/W Select framing reference input and sampling edge on selected REF3 for frame alignment 0x44 REF4/5_Frame_Phase_Align 7-0 R/W Select framing reference input and sampling edge on selected REF4 and REF5 for frame alignment 0x4A Synth_Index_Select 3-0 R/W Determine which synthesizer is selected for setting frequency value at register Synth_Freq_Value and adjusting phase skew at registers Synth_Skew_Adj 0x4B Synth_Freq_Value 17-0 R/W Selects synthesizer frequency value from 1MHz to 156.25MHz, in 1kHz steps, based on which synthesizer index is selected at the reg- ister Synth_Index_Select 0x4C 0x4D 0x4E Synth_Skew_Adj 11-0 R/W Adjust phase skew for the synthesizer with the index selected at register Synth_Index_Select 0x4F 0x50 CLK1_Signal_Level 0-0 R/W Select the signal level (LVDS or LVPECL) for clock output CLK1 0x51 CLK1_Sel 1-0 R/W Select synthesizer or enable tri-state for CLK1 0x52 CLK2_Sel 1-0 R/W Select synthesizer or enable tri-state for CLK2 0x59 CLK8K_Sel 6-0 R/W 8kHz frame pulse clock output duty cycle selection, signal inversion 0x5A CLK2K_Sel 6-0 R/W 2kHz frame pulse clock output duty cycle selection, signal inversion 0x5B Ref_Freq 14-0 R/W Select integer N for manually acceptable frequency at Nx8kHz; Enable auto detection of reference input frequency 0x5C 0x70 Field_Upgrade_Status 2-0 R Indicates the status of field upgrade process 0x71 Field_Upgrade_Data 7-0 R/W Load 7600 bytes of firmware configuration data 0x72 Field_Upgrade_Count 12-0 R Count byte numbers that have been loaded 0x73 0x74 Field_Upgrade_Start 7-0 W Write three values consecutively to start the field upgrade process 0x7F MCLK_Freq_Reset 7-0 R Select the frequency of the external oscillator Table 2: Register Map Addr Reg Name Bits Type Description |
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