전자부품 데이터시트 검색엔진 |
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TL432KM3 데이터시트(PDF) 7 Page - Cystech Electonics Corp. |
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TL432KM3 데이터시트(HTML) 7 Page - Cystech Electonics Corp. |
7 / 13 page CYStech Electronics Corp. Spec. No. : C112M3 Issued Date : 2015.09.10 Revised Date : Page No. : 7/13 TL432KA3/N3/M3 CYStek Product Specification Test Circuit-Small-Signal Gain and Phase Test Circuit-Stability 15k 8.25k PL432 232 Iz OUT GND 10£gF TL432 Applications Information - Stability Selection of load capacitance when using TL432K as a shunt regulator When the TL432K is used as a shunt regulator, two options for selection of CL(see diagram on page 6) are recommended for optimal stability: 1) No load capacitance across the device, decouple at the load. 2) Large capacitance across the device, optimal decoupling at the load. The reason for this is that TL432K exhibits instability with capacitances in the range of 47nF to 1μF (approx.) at light cathode currents(up to 0.5mA typical). The device is less stable the lower the cathode voltage has been set for. Therefore while the device will be perfectly stable operating at a cathode current of (say) 10mA with a 0.1μF capacitor across it, it will oscillate transiently during start-up as the cathode current passes through the instability region. Selecting a very low (or preferably, no) capaci- tance, or alternatively a high capacitance(such as 10μF) will avoid this issue altogether. Since the user will probably wish to have local decoupling at the load anyway, the most cost effective method is to use no capacitance at all directly across the device. PCB trace/via resistance and inductance prevent the local load decoupling from causing the oscillation during the transient start-up phase. Note : if the TL432K is located right at the load, so the load decoupling capacitor is directly across it, then this capacitor will have to be ≤1nF or ≥10μF. |
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