INV

NON INV

Error Amplifier Output

200 W

UC1825

Simplified Schematic

1

2

3

16

100

80

60

40

40

0

−20

f − Frequency − Hz

0

1 K

10 K 100 K

1 M

10 M 100 M

0

OPEN LOOP FREQUENCY RESPONSE

−90

−180

0

5

4

3

2

0

0.2

0.4

0.6

1

0.8

1

t − Time − ms

UNITY GAIN SLEW RATE

UC1825-SP

www.ti.com

SLUS870A – JANUARY 2009 – REVISED MARCH 2012

PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS

High speed circuits demand careful attention to layout and component placement. To ensure proper performance

of the UC1825 follow these rules:

1. Use a ground plane.

2. Damp or clamp parasitic inductive kick energy from the gate of driven MOSFETs. Do not allow the output

pins to ring below ground. A series gate resistor or a shunt 1-A Schottky diode at the output pin serves this

purpose.

Allow less than 1-cm of total lead length for each capacitor between the bypassed pin and the ground plane.

Figure 2. Error Amplifier

Copyright © 2009–2012, Texas Instruments Incorporated

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Product Folder Link(s): UC1825-SP