ISL29023

11

FN6691.4

May 1, 2014

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Suggested PCB Footprint

It is important that users check the “Surface Mount Assembly

Guidelines for Optical Dual Flat Pack No Lead (ODFN) Package”

before starting ODFN product board mounting, see TB477.

Board Mounting Consideration

For applications requiring the light measurement, the board

mounting location should be reviewed. The device uses an

Optical Dual Flat Pack No Lead (ODFN) package, which subjects

the die to mild stresses when the printed circuit (PC) board is

heated and cooled, which slightly changes the shape. Because of

these die stresses, placing the device in areas subject to slight

twisting can cause degradation of reference voltage accuracy. It

is normally best to place the device near the edge of a board, or

on the shortest side, because the axis of bending is most limited

in that location.

Layout Considerations

devices, it is intended to provide excellent performance even in

significantly noisy environments. There are only a few

considerations that will ensure best performance.

sources of noise. Use two power-supply decoupling capacitors,

as closely to the pin as possible to eliminate the stray

capacitance, which will greatly affect the performance of the

sensor.

Soldering Considerations

Convection heating is recommended for reflow soldering;

direct-infrared heating is not recommended. The plastic ODFN

package does not require a custom reflow soldering profile, and

is qualified to +260°C. A standard reflow soldering profile with a

+260°C maximum is recommended.

Temperature Coefficient

The limits stated for temperature coefficient (TC) are governed by

the method of measurement. The “Box” method is usually used

for specifying the temperature coefficient. The overwhelming

standard for specifying the temperature drift of a reference is to

evaluate the maximum voltage change over the specified

temperature range. This yields ppm/°C, and is calculated using

Equation 8:

where:

range.

range.

Digital Inputs and Termination

The ISL29023 digital inputs are guaranteed to CMOS levels. The

internal register is updated on the rising edge of the clock. To

minimize reflections, proper termination should be

implemented. If the lines driving the clock and the digital inputs

are 50Ω lines, then 50Ω termination resistors should be placed

as close to the sensor inputs as possible, connected to the digital

ground plane (if separate grounds are used).

Typical Circuit

A typical application for the ISL29023 is shown in Figure 1. The

compliant devices.

(EQ. 8)

TC

V

HIGH

V

LOW

–

V

NOMINAL

T

HIGH

T

LOW

–





----------------------------------------------------------------------------------

10

6



=

FIGURE 15. ISL29023 TYPICAL SYSTEM DIAGRAM

VDD

1

GND

2

REXT

3

INT

4

SCL

5

SDA

6

ISL29023

R1

R2

499k

C2

0.1µF

C1

10µF

2.25V TO 3.63V

MICROCONTROLLER

SDA

SCL

SCL

SDA

SCL

SDA

1.7V TO 3.63V

R3

INT