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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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LM27402 데이터시트(PDF) 3 Page - Texas Instruments |
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LM27402 데이터시트(HTML) 3 Page - Texas Instruments |
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3 / 48 page  EP 16 15 14 13 4 3 2 1 5 6 7 8 9 10 11 12 SS/TRACK FB COMP FADJ SW LG VDD GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 CS+ CS- SS/TRACK FB COMP FADJ SYNC EN PGOOD VIN GND VDD LG SW HG CBOOT EP LM27402 www.ti.com SNVS615J – JANUARY 2010 – REVISED JULY 2015 5 Pin Configuration and Functions PWP Package RUM Package 16-Pin HTSSOP 16-Pin WQFN Top View Top View Pin Functions PIN I/O(1) DESCRIPTION NAME HTSSOP WQFN High-side gate driver supply rail. Connect a 100-nF ceramic capacitor from CBOOT to CBOOT 16 13 P SW and a Schottky diode from VDD to CBOOT. Output of the internal error amplifier. The COMP voltage is compared to an internally COMP 5 3 O generated ramp at the PWM comparator to establish the duty cycle command. Current sense positive input. This pin is the noninverting input to the current-sense CS+ 1 16 I comparator. Current sense negative input. This pin is the inverting input to the current-sense CS– 2 15 I comparator. 10-µA of nominal offset current is provided for adjustable current limit setpoint. LM27402 enable pin. Apply a voltage typically higher than 1.17 V to EN and the LM27402 will begin to switch if VIN and VDD have exceeded their UVLO thresholds. EN 8 5 I A hysteresis of 100 mV on EN provides noise immunity. EN is internally tied to VDD through a 2-µA pullup current source. EN must not exceed the voltage on VDD. Frequency adjust input. The switching frequency is programmable between 200 kHz FADJ 6 4 I and 1.2 MHz by connecting a resistor between FADJ and GND. Feedback input. Inverting input to the error amplifier to set the output voltage and FB 4 2 I compensate the voltage-mode control loop. Common ground connection. This pin provides the power and signal return GND 11 9 G connections for analog functions, including low-side MOSFET gate return, soft-start capacitor, and frequency adjust resistor. HG 15 14 O High-side MOSFET gate drive output. LG 13 11 O Low-side MOSFET gate drive output. Power Good monitor output. This open-drain output goes low during overcurrent, short-circuit, UVLO, output overvoltage and undervoltage, overtemperature, or when PGOOD 9 8 O the output is not regulated (such as an output prebias). An external pullup resistor to VDD or to an external rail is required. Included is a 20- μs deglitch filter. The PGOOD voltage should not exceed 5.5 V. (1) P= Power, G = Ground, I = Input, O = Output Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LM27402 |
유사한 부품 번호 - LM27402_15 |
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유사한 설명 - LM27402_15 |
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