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ML2036CP 데이터시트(PDF) 9 Page - Micro Linear Corporation |
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ML2036CP 데이터시트(HTML) 9 Page - Micro Linear Corporation |
9 / 12 page ML2036 9 Figure 6. Power Down and Inhibit Mode Waveforms. VOS 0V POWER DOWN MODE INHIBIT MODE VOS 0 V VX SCK SID LATI 01234567 89 10 11 12 131415 |VX| = VPEAK 256 , FOR fOUT ≤ fCLK 2048 |VX| ≤ VPEAK 256 + VPEAK SIN 8 π fOUT fCLK π 512 + FOR fOUT > fCLK 2048 Table 1. Three Level PDN-INH Functions. PDN–INH PDN–INH DATA IN MODE PIN SHIFT REG. LATI SINE WAVE OUTPUT PDN(1) VI1, Logic "0" X X VOUT = 0V (10k W to AGND) Inhibit VI2, Inhibit State All 0‘s Logic "1" VOUT goes to approximately VOS Voltage, VSS to at the next VOS crossing VSS + 0.5V (See Figure 6) PDN(1) VI3, Logic "1" All 0‘s Logic "1" VOUT = 0V (10k W to AGND) Note 1: In the power down mode, the oscillator, CLK OUT 1 and CLK OUT 2, shift register, and data latch are all functional. |
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