N01S830HA, N01S830BA

http://onsemi.com

4

DEVICE OPERATIONS

Read Operation

The serial SRAM Read operation is started by by enabling

CS low. First, the 8-bit Read instruction is transmitted to the

device through the SI (or SIO0-3) pin(s) followed by the

24-bit address with the 7 MSBs of the address being “don’t

care” bits and ignored. In SPI mode, after the READ

instruction and address bits are sent, the data stored at that

address in memory is shifted out on the SO pin after the

output valid time. Additional “dummy” clock cycles (four in

DUAL and two in QUAD) are required to follow the

instruction and address inputs prior to the data being driven

out on the SIO0-3 pins while operating in these two modes.

By continuing to provide clock cycles to the device, data

can continue to be read out of the memory array in

sequentially. The internal address pointer is automatically

incremented to the next higher address after each byte of

data is read out until the highest memory address is reached.

When the highest memory address is reached, 1FFFFh, the

address pointer wraps to the address 00000h. This allows the

read cycles to be continued indefinitely. All Read operations

are terminated by pulling CS high.

Figure 2. SPI Read Sequence (Single Byte)

CS

Instruction

SI

04

3

25

16

9

810

7

11

SCK

23 22 21 20

21

0

7

65

43

21

0

High−Z

24−bit address

Data Out

SO

29

31

30

32

36 37 38 39

34 35

33

000

0

00

1

1

Figure 3. SPI Read Sequence (Sequential Bytes)

CS

Instruction

SI

04

3

25

16

9

810

7

11

SCK

23 22 21 20

210

7

65

43

21

0

High−Z

24−bit address

Data Out from ADDR 1

SO

29

31

30

32

36 37 38 39

34 35

33

000

0

0

011

7

65

43

210

Data Out from ADDR 2

7

65

43

21

0

7

6

543

210

...

40

42

41

43

47 48 49 50

45 46

44

51

53

52

54 55

Don’t Care

Don’t Care

ADDR 1

Data Out from ADDR 3

Data Out from ADDR n