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TL4050C20-Q1 데이터시트(PDF) 10 Page - Texas Instruments |
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TL4050C20-Q1 데이터시트(HTML) 10 Page - Texas Instruments |
10 / 20 page 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 1 2 3 4 5 6 7 VREF AIN0 AIN1 AIN2 AGND DB11 DB10 DB9 DB8 DB7 DB6 DB5 DGND AIN3 VANA 2.2 mF A1 A0 CLK DB0 DB1 DB2 DB3 DB4 VDIG BUSY WR CS RD 3.2-MHz Clock BUSY Output Write Input Read Input 5-V Analog Supply 10 mF + + + 0.1 mF ADS7842 TL4050B41-Q1 909 0 V to VREF 5 V 1-Hz Rate VZ TL4050-Q1 RS VIN TL4050-Q1 SLOS588F – JUNE 2008 – REVISED APRIL 2013 www.ti.com APPLICATION INFORMATION Figure 7. Start-Up Test Circuit Output Capacitor The TL4050-Q1 does not require an output capacitor across cathode and anode for stability. However, in an application using an output bypass capacitor, the TL4050-Q1 is stable with all capacitive loads. SOT-23-3 Pin Connections There is a parasitic Schottky diode connected between pins 2 and 3 of the SOT-23-3 packaged device. Thus, pin 3 of the SOT-23-3 package must be left floating or connected to pin 2. Use With ADCs or DACs The design of the TL4050x41-Q1 is as a cost-effective voltage reference, as required in 12-bit data-acquisition systems. For 12-bit systems operating from 5-V supplies, such as the ADS7842 (see Figure 8), the TL4050x41- Q1 (4.096 V) permits operation with an LSB of 1 mV. Figure 8. Data-Acquisition Circuit With TL4050x41-Q1 10 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated |
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