전자부품 데이터시트 검색엔진 |
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DM54173W 데이터시트(PDF) 1 Page - National Semiconductor (TI) |
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DM54173W 데이터시트(HTML) 1 Page - National Semiconductor (TI) |
1 / 6 page TLF6556 June 1989 54173DM54173DM74173 TRI-STATE Quad D Registers General Description These four-bit registers contain D-type flip-flops with totem- pole TRI-STATE outputs capable of driving highly capaci- tive or low-impedance loads The high-impedance state and increased high-logic-level drive provide these flip-flops with the capability of driving the bus lines in a bus-organized sys- tem without need for interface or pull-up components Gated enable inputs are provided for controlling the entry of data into the flip-flops When both data-enable inputs are low data at the D inputs are loaded into their respective flip- flops on the next positive transition of the buffered clock input Gate output control inputs are also provided When both are low the normal logic states of the four outputs are available for driving the loads or bus lines The outputs are disabled independently from the level of the clock by a high logic level at either output control input The outputs then present a high impedance and neither load nor drive the bus line Detailed operation is given in the function table To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels the output con- trol circuitry is designed so that the average output disable times are shorter than the average output enable times Features Y TRI-STATE outputs interface directly with system bus Y Gated output control lines for enabling or disabling the outputs Y Fully independent clock elminates restrictions for oper- ating in one of two modes Parallel load Do nothing (hold) Y For application as bus buffer registers Y Typical propagation delay 18 ns Y Typical frequency 30 MHz Y Typical power dissipation 250 mW Y Alternate MilitaryAerospace device (54173) is avail- able Contact a National Semiconductor Sales Office Distributor for specifications Connection Diagram Dual-In-Line Package TLF6556 – 1 Order Number 54173DMQB 54173FMQB DM54173J DM54173W or DM74173N See NS Package Number J16A N16E or W16A Function Table Inputs Output Clear Clock Data Enable Data Q G1 G2 D HX X X X L LL X X X Q0 L u HX X Q0 L u XH X Q0 L u LL L L L u LL H H When either M or N (or both) is (are) high the output is disabled to the high-impedance state however sequential operation of the flip-flops is not affected H e high level (steady state) L e low level (steady state) u e low-to-high level transition X e don’t care (any input including transitions) Q0 e the level of Q before the indicated steady state input conditions were established TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation RRD-B30M105Printed in U S A |
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