전자부품 데이터시트 검색엔진 |
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74LVX08 데이터시트(PDF) 1 Page - Fairchild Semiconductor |
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74LVX08 데이터시트(HTML) 1 Page - Fairchild Semiconductor |
1 / 7 page © 1993 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LVX08 Rev. 1.5.0 1 June 2014 74LVX08 Low Voltage Quad 2-Input AND Gate Features • Input Voltage Level Translation from 5 V to 3 V • Ideal for Low-power / Low-Noise 3.3 V Applications • Guaranteed Simultaneous Switching Noise Level and Dynamic threshold Performance Ordering Information All packages are lead free per JEDEC: J-STD-020B standard. Pin Description Part Number Top Mark Package Packing Method Packing Description 74LVX08M LVX08 SOIC 14L Rail 14-Lead Small Outline Integrated Circuit, JEDEC MS-012, 0.150 inch Narrow 74LVX08MX LVX08 SOIC 14L Tape and Reel 14-Lead Small Outline Integrated Circuit, JEDEC MS-012, 0.150 inch Narrow 74LVX08MTCX LVX08 TSSOP 14L Tape and Reel 14-Lead Thin Shrink Small Outline Package, JEDEC MO-153, 4.4 mm Wide Connection Diagram Logic Symbol Pin Names Description An, Bn Inputs On Outputs IEEE/IEC Description The LVX08 contains four 2-input AND gates. The inputs tolerate voltages up to 7 V allowing the interface of 5 V systems to 3 V systems. |
유사한 부품 번호 - 74LVX08_14 |
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유사한 설명 - 74LVX08_14 |
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