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54ACT323L 데이터시트(PDF) 2 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
부품명 54ACT323L
상세설명  8-Bit Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins
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제조업체  NSC [National Semiconductor (TI)]
홈페이지  http://www.national.com
Logo NSC - National Semiconductor (TI)

54ACT323L 데이터시트(HTML) 2 Page - National Semiconductor (TI)

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Connection Diagrams
Functional Description
The ’ACT323 contains eight edge-triggered D-type flip-flops
and the interstage logic necessary to perform synchronous
reset, shift left, shift right, parallel load and hold operations.
The type of operation is determined by S
0 and S1 as shown
in the Mode Select Table. All flip-flop outputs are brought out
through TRI-STATE buffers to separate I/O pins that also
serve as data inputs in the parallel load mode. Q
0 and Q7 are
also brought out on other pins for expansion in serial shifting
of longer words.
A LOW signal on SR overrides the Select inputs and allows
the flip-flops to be reset by the next rising edge of CP. All
other state changes are also initiated by the LOW-to-HIGH
CP transition. Inputs can change when the clock is in either
state provided only that the recommended setup and hold
times, relative to the rising edge of CP, are observed.
A HIGH signal on either OE
1 or OE2 disables the TRI-STATE
buffers and puts the I/O pins in the high impedance state. In
this condition the shift, load, hold and reset operations can
still occur. The TRI-STATE buffers are also disabled by HIGH
signals on both S
0 and S1 in preparation for a parallel load
operation.
Mode Select Table
Inputs
Response
SR
S
1
S
0
CP
LX
X
N
Synchronous Reset; Q
0–Q7 = LOW
HH
H
N
Parallel Load; I/O
n→Qn
HL
H
N
Shift Right; DS
0→Q0,Q0→Q1, etc.
HH
L
N
Shift Left; DS
7→Q7,Q7→Q6, etc.
H
L
L
X
Hold
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
N = LOW-to-HIGH Clock Transition
Pin Assignment for
DIP and Flatpak
DS100328-2
Pin Assignment
for LCC
DS100328-3
www.national.com
2


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