전자부품 데이터시트 검색엔진 |
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SI554 데이터시트(PDF) 3 Page - Silicon Laboratories |
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SI554 데이터시트(HTML) 3 Page - Silicon Laboratories |
3 / 15 page Si554 Rev. 1.1 3 Table 3. CLK± Output Frequency Characteristics Parameter Symbol Test Condition Min Typ Max Units Nominal Frequency1,2,3 fO LVDS/CML/LVPECL 10 — 945 MHz CMOS 10 — 160 MHz Temperature Stability1,4 TA = –40 to +85 °C –20 –50 –100 — — — +20 +50 +100 ppm Absolute Pull Range1,4 APR ±12 — ±375 ppm Aging Frequency drift over first year. — — ±3 ppm Frequency drift over 15 year life. — — ±10 Power up Time5 tOSC —— 10 ms Settling Time After FS[1:0] Change tFRQ Both FS[1] and FS[0] changing simultaneously —— 20 ms Notes: 1. See Section 3. "Ordering Information" on page 10 for further details. 2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz. 3. Nominal output frequency set by VCNOM =VDD/2. 4. Selectable parameter specified by part number. 5. Time from power up or tristate mode to fO (to within ±1 ppm of fO). Table 4. CLK± Output Levels and Symmetry Parameter Symbol Test Condition Min Typ Max Units LVPECL Output Option1 VO mid-level VDD – 1.42 — VDD – 1.25 V VOD swing (diff) 1.1 — 1.9 VPP VSE swing (single-ended) 0.55 — 0.95 VPP LVDS Output Option2 VO mid-level 1.125 1.20 1.275 V VOD swing (diff) 0.5 0.7 0.9 VPP CML Output Option2 VO 2.5/3.3 V option mid-level — VDD – 1.30 — V 1.8 V option mid-level — VDD – 0.36 — V VOD 2.5/3.3 V option swing (diff) 1.10 1.50 1.90 VPP 1.8 V option swing (diff) 0.35 0.425 0.50 VPP CMOS Output Option3 VOH IOH =32mA 0.8 x VDD — VDD V VOL IOL =32mA — — 0.4 Rise/Fall time (20/80%) tR, tF LVPECL/LVDS/CML — — 350 ps CMOS with CL =15pF — 1 — ns Symmetry (duty cycle) SYM LVPECL: VDD – 1.3 V (diff) LVDS: 1.25 V (diff) CMOS: VDD/2 45 — 55 % Notes: 1. 50 to V DD – 2.0 V. 2. Rterm = 100 (differential). 3. CL = 15 pF |
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