SI5320 datasheet(11/34 Pages) SILABS

부품명	SI5320

상세설명	SONET/SDH PRECISION CLOCK MULTIPLIER IC

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제조업체	SILABS [Silicon Laboratories]

홈페이지	http://www.silabs.com

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Si5320

Rev. 2.5

11

CLKOUT Peak-Peak Jitter Generation

FEC[1:0] = 00

JGEN(PP)

12 kHz to 20 MHz

—

6.8

10.0

ps

50 kHz to 80 MHz

—

3.7

5.0

ps

Jitter Transfer Bandwidth (see Figure 6)

FBW

BW = 3200 Hz

—

3200

—

Hz

Wander/Jitter Transfer Peaking

JP

< 3200 Hz

—

0.05

0.1

dB

Wander/Jitter at 3200 Hz Bandwidth

(BWSEL[1:0] = 00 and DBLBW = 0)

Jitter Tolerance (see Figure 7)

JTOL(PP)

f= 32 Hz

1000

—

—ns

f= 320Hz

100

—

—ns

f = 3200 Hz

10

—

—ns

CLKOUT RMS Jitter Generation

FEC[1:0] = 00

JGEN(RMS)

12 kHz to 20 MHz

—

0.86

1.2

ps

50 kHz to 80 MHz

—

0.29

0.4

ps

CLKOUT RMS Jitter Generation

FEC[1:0] = 01, 10

JGEN(RMS)

12 kHz to 20 MHz

—

0.79

1.2

ps

50 kHz to 80 MHz

—

0.28

0.4

ps

CLKOUT Peak-Peak Jitter Generation

FEC[1:0] = 00

JGEN(PP)

12 kHz to 20 MHz

—

7.7

10.0

ps

50 kHz to 80 MHz

—

3.9

5.0

ps

CLKOUT Peak-Peak Jitter Generation

FEC[1:0] = 01, 10

JGEN(PP)

12 kHz to 20 MHz

—

7.2

10.0

ps

50 kHz to 80 MHz

—

4.0

5.0

ps

Jitter Transfer Bandwidth (see Figure 6)

FBW

BW = 3200 Hz

—

3200

—Hz

Wander/Jitter Transfer Peaking

JP

< 3200 Hz

—

0.05

0.1

dB

Wander/Jitter at 6400 Hz Bandwidth

(BWSEL[1:0] = 00 and DBLBW = 1)

Jitter Tolerance (see Figure 7)

f = 64 Hz

500

—

ns

f= 640Hz

50

—

ns

f= 6400 Hz

5

—

ns

CLKOUT RMS Jitter Generation

FEC[1:0] = 00

JGEN(RMS)

12 kHz to 20 MHz

—

0.7

1.0

ps

50 kHz to 80 MHz

—

0.25

0.3

ps

CLKOUT Peak-Peak Jitter Generation

FEC[1:0] = 00

JGEN(PP)

12 kHz to 20 MHz

—

6.6

9.0

ps

50 kHz to 80 MHz

—

3.8

5.0

ps

Table 4. AC Characteristics (PLL Performance Characteristics) (Continued)

(VDD33 = 3.3 V ±5%, TA = –20 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max Unit

Notes:

1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient.

2. For reliable device operation, temperature gradients should be limited to 10 °C/min.

3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms of

nanoseconds per millisecond. The equivalent ps/

s unit is used here since the maximum phase transient magnitude for the

Si5320 (tPT_MTIE) never reaches one nanosecond.

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