전자부품 데이터시트 검색엔진 |
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SI5369B-C-GQ 데이터시트(PDF) 1 Page - Silicon Laboratories |
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SI5369B-C-GQ 데이터시트(HTML) 1 Page - Silicon Laboratories |
1 / 84 page Rev. 1.0 1/13 Copyright © 2013 by Silicon Laboratories Si5369 Si5369 A NY-F REQUENCY P RECISION C LOCK M ULTIPLIER/J ITTER A TTENUATOR Features Applications Description The Si5369 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps rms jitter performance. The Si5369 accepts four clock inputs ranging from 2 kHz to 710 MHz and generates five clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The device provides virtually any frequency translation combination across this operating range. The outputs are divided down separately from a common source. The Si5369 input clock frequency and clock multiplication ratio are programmable through an I2C or SPI interface. The Si5369 is based on Silicon Laboratories' third-generation DSPLL® technology, which provides any-frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5 ,or 3.3 V supply, the Si5369 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications. Generates any frequency from 2 kHz to 945 MHz and select frequencies to 1.4 GHz from an input frequency of 2 kHz to 710 MHz Ultra-low jitter clock outputs with jitter generation as low as 300 fs rms (12 kHz–20 MHz) Integrated loop filter with selectable loop bandwidth (4 Hz to 525 Hz) Meets OC-192 GR-253-CORE jitter specifications Four clock inputs with manual or automatically controlled hitless switching and phase build-out Supports holdover and freerun modes of operation SONET frame sync switching and regeneration Five clock outputs with selectable signal format (LVPECL, LVDS, CML, CMOS) Support for ITU G.709 and custom FEC ratios (253/226, 239/237, 255/238, 255/237, 255/236) LOL, LOS, FOS alarm outputs Digitally-controlled output phase adjust I2C or SPI programmable settings On-chip voltage regulator for 1.8 V ±5%, 2.5 V ±10%, or 3.3 V ±10% operation Small size: 14 x 14 mm 100-pin TQFP Pb-free, RoHS compliant SONET/SDH OC-48/STM-16/OC- 192/STM-64 line cards GbE/10GbE, 1/2/4/8/10G FC line cards ITU G.709 and custom FEC line cards Wireless repeaters/wireless backhaul Data converter clocking OTN/WDM Muxponder, MSPP, ROADM line cards SONET/SDH + PDH clock synthesis Test and measurement Synchronous Ethernet Broadcast video Ordering Information: See page 78. |
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