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SI52143 데이터시트(PDF) 11 Page - Silicon Laboratories

부품명 SI52143
상세설명  PCI-EXPRESS GEN 1, GEN 2, & GEN 3 QUAD OUTPUT CLOCK GENERATOR WITH 25 MHZ REFERENCE CLOCK
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Si52143
Rev 1.3
11
4. Control Registers
4.1. I2C Interface
To enhance the flexibility and function of the clock synthesizer, an I2C interface is provided. Through the I2C
Interface, various device functions are available, such as individual clock enablement. The registers associated
with the I2C Interface initialize to their default setting at power-up. The use of this interface is optional. Clock device
register changes are normally made at system initialization, if any are required. Power management functions can
only be programed in program mode and not in normal operation modes.
4.2. Data Protocol
The clock driver I2C protocol accepts byte write, byte read, block write, and block read operations from the
controller. For block write/read operation, access the bytes in sequential order from lowest to highest (most
significant bit first) with the ability to stop after any complete byte is transferred. For byte write and byte read
operations, the system controller can access individually indexed bytes.
The block write and block read protocol is outlined in Table 5 while Table 6 outlines byte write and byte read
protocol. The slave receiver address is 11010110 (D6h).
Table 5. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Bit
Description
Bit
Description
1
Start
1
Start
8:2
Slave address—7 bits
8:2
Slave address—7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
18:11
Command Code—8 bits
18:11
Command Code—8 bits
19
Acknowledge from slave
19
Acknowledge from slave
27:20
Byte Count—8 bits
20
Repeat start
28
Acknowledge from slave
27:21
Slave address—7 bits
36:29
Data byte 1—8 bits
28
Read = 1
37
Acknowledge from slave
29
Acknowledge from slave
45:38
Data byte 2—8 bits
37:30
Byte Count from slave—8 bits
46
Acknowledge from slave
38
Acknowledge
....
Data Byte /Slave Acknowledges
46:39
Data byte 1 from slave—8 bits
....
Data Byte N—8 bits
47
Acknowledge
....
Acknowledge from slave
55:48
Data byte 2 from slave—8 bits
....
Stop
56
Acknowledge
....
Data bytes from slave/Acknowledge
....
Data Byte N from slave–8 bits
....
NOT Acknowledge
....
Stop


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