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CDCLVP111VF 데이터시트(PDF) 1 Page - Texas Instruments |
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CDCLVP111VF 데이터시트(HTML) 1 Page - Texas Instruments |
1 / 29 page LVPECL Reference Generator VEE VCC VCC VCC VCC VCC 10 10 QP(9...0) QN(9...0) CLKP0 CLKN0 CLKP1 CLKN1 CLK_SEL VBB + + CDCLVP111 Product Folder Sample & Buy Technical Documents Tools & Software Support & Community CDCLVP111 SCAS859F – JANUARY 2009 – REVISED JUNE 2015 CDCLVP111 Low-Voltage 1:10 LVPECL With Selectable Input Clock Driver 1 Features 3 Description The CDCLVP111 clock driver distributes one 1 • Distributes One Differential Clock Input Pair differential clock pair of LVPECL input, (CLK0, CLK1) LVPECL to 10 Differential LVPECL to ten pairs of differential LVPECL clock (Q0, Q9) • Fully Compatible With LVECL and LVPECL outputs with minimum skew for clock distribution. The • Supports a Wide Supply Voltage Range from CDCLVP111 can accept two clock sources into an input multiplexer. The CDCLVP111 is specifically 2.375 V to 3.8 V designed for driving 50- Ω transmission lines. When • Selectable Clock Input Through CLK_SEL an output pin is not used, leaving it open is • Low-Output Skew (Typical 15 ps) for Clock- recommended to reduce power consumption. If only Distribution Applications one of the output pins from a differential pair is used, the other output pin must be identically terminated to – Additive Jitter Less Than 1 ps 50 Ω. – Propagation Delay Less Than 350 ps The VBB reference voltage output is used if single- – Open Input Default State ended input operation is required. In this case, the – LVDS, CML, SSTL Input Compatible VBB pin should be connected to CLK0 and bypassed • VBB Reference Voltage Output for Single-Ended to GND through a 10-nF capacitor. Clocking However, for high-speed performance up to 3.5 GHz, • Available in a 32-Pin LQFP and QFN Package the differential mode is strongly recommended. • Frequency Range From DC to 3.5 GHz The CDCLVP111 device is characterized for • Pin-to-Pin Compatible With MC100 Series EP111, operation from –40°C to 85°C. ES6111, LVEP111, PTN1111 Device Information(1) 2 Applications PART NUMBER PACKAGE BODY SIZE (NOM) • Designed for Driving 50- Ω Transmission Lines VQFN (32) 5.00 mm × 5.00 mm CDCLVP111 LQFP (32) 7.00 mm × 7.00 mm • High Performance Clock Distribution (1) For all available packages, see the orderable addendum at the end of the data sheet. Functional Block Diagram 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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