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SL2304NZZI-1 데이터시트(PDF) 3 Page - Silicon Laboratories |
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SL2304NZZI-1 데이터시트(HTML) 3 Page - Silicon Laboratories |
3 / 9 page Rev 2.1, May 6, 2008 Page 3 of 9 SL2304NZ General Description The SL2304NZ is a low skew, jitter and power fanout Buffer designed to produce up to four (4) clock outputs from one (1) reference input clock, for high speed clock distribution, including PCI/PCI-X applications. Input and output Frequency Range The input and output frequency is the same (1x) for SL2304NZ-1 and SL2304NZ-1Z and operates from DC to 140MHz clock range with up to 25pF output load. OE (Output Enable) Function The only difference between SL2304-1 and SL2304NZ- 1Z is the OE logic implementation. When OE=0, SL2404NZ-1 outputs are disabled and outputs are at Logic Low. In the case of SL2304NZ-1Z the outputs are at High-Z. Refer to the Available OE Logic Configuration Table. 1 below. Output Clock Skew All outputs should drive the similar load to achieve output- to-output skew and input-to-output delay specifications as given in the switching electrical tables. Power Supply Range (VDD) The SL2304NZ is designed to operate 3.3V+/-10% (3.63V- max to 2.97V-min) VDD power supply range. An internal on-chip voltage regulator is used to provide to constant power supply of 1.8V, leading to a consistent and stable electrical performance in terms of skew and jitter. The SL2304NZ I/O is powered by using VDD. Refer to SL23EP04NZ products for DC to 220MHz-max frequency range, 2.5V to 3.3V power supply operation, improved skew, jitter and higher drive options. Contact SLI for 1.8V power supply Fan-Out Buffer and ZDB products. CLKIN (Pin-1) OE (Pin-2) SL2304NZ-1 CLKOUT [1:4] SL2304NZ-1Z CLKOUT [1:4] Low Low Low High-Z High Low Low High-Z Low High Low Low High High High High Table 1. Available SL2304 CLKIN and OE Logic Configurations |
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유사한 설명 - SL2304NZZI-1 |
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