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SL2305ZI-1 데이터시트(PDF) 1 Page - Silicon Laboratories

부품명 SL2305ZI-1
상세설명  Low Jitter and Skew 10 to 140 MHz Zero Delay Buffer
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제조업체  SILABS [Silicon Laboratories]
홈페이지  http://www.silabs.com
Logo SILABS - Silicon Laboratories

SL2305ZI-1 데이터시트(HTML) 1 Page - Silicon Laboratories

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Rev 2.1, October 22, 2007
Page 1 of 11
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
www.silabs.com
SL2305
Key Features
• 10 to 140 MHz operating frequency range
• Low output clock jitter:
- 140 ps-max c-c-j at 66 MHz
• Low output-to-output skew: 150 ps-max
• Low product-to-product skew: 400 ps-max
• 3.3 V power supply range
• Low power dissipation:
- 14 mA-max at 66MHz
- 26 mA-max at 133 MHz
• One input drives 5 outputs organized as 4+1
• SpreadThru™ PLL that allows use of SSCG
• Standard and High-Drive options
• Available in 8-pin SOIC and TSSOP packages
• Available in Commercial and Industrial grades
Applications
• Printers and MFPs
• Digital Copiers
• PCs and Work Stations
• DTV
• Routers, Switchers and Servers
• Digital Embeded Systems
Description
The SL2305 is a low skew, low jitter and low power Zero
Delay Buffer (ZDB) designed to produce up to five (5) clock
outputs from one (1) reference input clock for high speed
clock distribution applications. The product has an on-chip
PLL which locks to the input clock at CLKIN and receives its
feedback internally from the CLKOUT pin.
The SL2305 is available with two (2) drive strength versions.
The -1 is the standard-drive version and -1H is the high-
drive version.
The SL2305 high-drive version operates up to 140MHz and
the standard drive version -1 operates up to 100.
The SL2305 enter into Power-Down (PD) mode if the input
at CLKIN is DC (0 to VDD). In this power-down state all five
(5) outputs are tri-stated and the PLL is turned off leading to
less than 12
μA-max of power supply current draw.
Benefits
• Up to five (5) distribution of input clock
• Standard and High-Drive levels to control impedance
level, frequency range and EMI
• Low jitter and skew
• Low power dissipation
• Low cost
Block Diagram
PLL
VDD
GND
CLKIN
CLKOUT
CLK1
CLK2
CLK3
CLK4
Low Jitter and Skew 10 to 140 MHz Zero Delay Buffer (ZDB)


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