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DLP2010 데이터시트(PDF) 11 Page - Texas Instruments |
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DLP2010 데이터시트(HTML) 11 Page - Texas Instruments |
11 / 41 page DLP2010 www.ti.com DLPS046A – JULY 2014 – REVISED APRIL 2015 6.7 Timing Requirements Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted. MIN NOM MAX UNIT LPSDR tR Rise slew rate(1) (30% to 80%) × VDD, Figure 3 1 3 V/ns tV Fall slew rate(1) (70% to 20%) × VDD, Figure 3 1 3 V/ns tR Rise slew rate(2) (20% to 80%) × VDD, Figure 3 0.25 V/ns tF Fall slew rate(2) (80% to 20%) × VDD, Figure 3 0.25 V/ns tC Cycle time LS_CLK, Figure 2 7.7 8.3 ns tW(H) Pulse duration LS_CLK 3.1 ns 50% to 50% reference points,Figure 2 high tW(L) Pulse duration LS_CLK 3.1 ns 50% to 50% reference points, Figure 2 low tSU Setup time LS_WDATA valid before LS_CLK ↑, Figure 2 1.5 ns tH Hold time LS_WDATA valid after LS_CLK ↑, Figure 2 1.5 ns tWINDOW Window time(1)(3) Setup time + Hold time, Figure 2 3 ns tDERATING For each 0.25 V/ns reduction in slew rate below 0.35 ns Window time derating(1)(3) 1 V/ns, Figure 5 SubLVDS tR Rise slew rate 20% to 80% reference points, Figure 4 0.7 1 V/ns tF Fall slew rate 80% to 20% reference points, Figure 4 0.7 1 V/ns tC Cycle time LS_CLK, Figure 6 1.61 1.67 ns tW(H) Pulse duration DCLK high 50% to 50% reference points, Figure 6 0.71 ns tW(L) Pulse duration DCLK low 50% to 50% reference points, Figure 6 0.71 ns D(0:3) valid before tSU Setup time DCLK ↑ or DCLK ↓, Figure 6 D(0:3) valid after tH Hold time DCLK ↑ or DCLK ↓, Figure 6 tWINDOW Window time Setup time + Hold time, Figure 6,Figure 7 0.3 ns tLVDS- Power-up receiver(4) 2000 ns ENABLE+REFGEN (1) Specification is for LS_CLK and LS_WDATA pins. Refer to LPSDR input rise slew rate and fall slew rate in Figure 3. (2) Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in Figure 3. (3) Window time derating example: 0.5-V/ns slew rate increases the window time by 0.7 ns, from 3 to 3.7 ns. (4) Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: DLP2010 |
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