LED_SEL(2)

I2C

DC

Supplies

4

24/16/8

BAT

1.0V

WVGA

DDR DMD

nHD/WVGA

DDR DMD

SYSPWR

L1

RESETZ

3

DLPC2607

L2

1.8V

28

CLRL

DATA

PROJ_ON

PROJ_ON

2.3V-5.5V

SPI(4)

Mobile SDRAM

Connector

CMP_OUT

Flash

Projector Module Electronics

BIAS, RST, OFS

DATA

CTRL

Thermistor

DDR

DDR

RGB

PWM_IN

PAD1000

Analog

ASIC

PWR_EN

VLED

BLUE

Parallel or

BT.656

Application

Processor

1.0V

1.8V

VCORE

VIO

GREEN

RED

Illumination

Optics

L5

L6

Dual

Reg.

INIT_DONE

GPIO4

GPIO5

INTZ

PARKZ

Product

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Sample &

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Technical

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Software

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DLPC2607

DLPS030C – DECEMBER 2013 – REVISED NOVEMBER 2015

DLPC2607 DLP PICO Processor 2607 ASIC

1 Features

Flip

–

Display Image Rotation

1

•

Supports Reliable Operation of the 0.2-nHD,

0.24-VGA, and 0.3-WVGA DMDs

–

Flash-Based Configuration Batch Files

•

Multi-Mode, 24-Bit Input Pixel Interfaces:

–

I/F Sleep Still Image Power Savings Mode

–

Supports Parallel or BT656 Bus Protocol

•

Test Support:

–

Supports Input Sizes from QVGA Through

–

Built-In Test Pattern Generation

WVGA

–

JTAG With Boundary Scan Test Support

–

Supports 1- to 60-Hz Frame Rates

2 Applications

–

Supports Pixel Clock up to 33.5 MHz

•

Embedded Mobile Projection

–

Supports Landscape and Portrait Orientations

–

Smartphone

–

Support 8-, 16-, 18-, and 24-Bit Bus Options

–

Tablet

–

Supports 3 Input Color Bit-Depth Options:

–

Camera

–

RGB888, YCrCb888

–

Laptop

–

RGB666, YCrCb666

•

Mobile Accessories

–

RGB565, 4:2:2 YCrCb

•

Wearable (Near-Eye) Displays

•

Pixel Data Processing:

•

Battery-Operated Projectors

–

Image Resizing (Scaling)

–

Frame Rate Conversion

3 Description

–

Color Coordinate Adjustment

The DLPC2607 is a low power DLP™ digital

–

Automatic Gain Control

controller for battery powered display applications.

–

Programmable Degamma

The controller supports reliable operation of 0.3-

WVGA,

0.24-VGA

and

0.2-nHD

DMDs.

The

–

Spatial-Temporal Multiplexing (Dithering)

DLPC2607 controller provides a convenient, multi-

–

Video Processing Support:

functional interface between system electronics and

–

Color Space Conversion

the DMD, enabling small form factor and low power

displays.

–

4:2:2 to 4:4:4 Chroma Interpolation

–

Field Scaled De-Interlacing

Device Information(1)

•

Packaged in a 176-Pin, 0.4-mm Pitch, VFBGA

PART NUMBER

PACKAGE

BODY SIZE (NOM)

•

External Memory Support:

DLPC2607

VFBGA (176)

7.00 mm × 7.00 mm

–

166-MHz Mobile DDR SDRAM

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

–

33.3-MHz Serial Flash

•

WVGA, VGA, and nHD DMD Display Support

–

DMD Bit-Plane Generation and Formatting

–

Programmable Bit-Plane Display Sequencer

(Controls the LED Enables and DMD Loading)

–

76.2-MHz Double Data Rate (DDR) DMD I/F

–

Pulse-Width Modulation (PWM) for Mirrors:

–

Auto DMD Parking at Power-Down

–

24-Bit Bit-Depth on DMD

•

System Control:

–

–

Programmable Splash Screens

–

Programmable LED Current Control

–

DMD Power and Mirror Driver Control

–

DMD Horizontal and Vertical Display Image

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.