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TS1108-20IQT163 데이터시트(PDF) 5 Page - Silicon Laboratories |
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TS1108-20IQT163 데이터시트(HTML) 5 Page - Silicon Laboratories |
5 / 23 page 2.3 Sign Output The TS1108 SIGN output indicates the load current’s direction. The SIGN output is a logic HIGH when M1 is conducting current (VRS+ > VRS–). Alternatively, the SIGN output is a logic LOW when M2 is conducting current (VRS– > VRS+). The SIGN comparator’s transfer characteristic is illustrated in Figure 1. Unlike other current-sense amplifiers that implement an OUT/SIGN arrangement, the TS1108 exhibits no “dead zone” at ILOAD switchover. Figure 2.2. TS1108 Sign Output Transfer Characteristic 2.4 Integrator + Comparator The TS1108 Coulomb Counter function utilizes an Integrator and a Comparator plus a 90 µs Monoshot. The CSA’s buffered output is applied to the integrator’s input. This signal is integrated by the comparator until it reaches a level that trips the comparator. The compa- rator’s trip level is determined by the voltage applied to the comparator’s non-inverting terminal, CIN+. The Monoshot produces a 90 µs output pulse at COUT and the integrator is reset. Therefore, each COUT 90 µs pulse represents an accumulation of coulombs (Please refer to the equations in 2.6 Coulomb Counter). The TS1108 Integrator works best when the 90 μs Monoshot represents less than 2% of the total integration period. Therefore, the minimum integration time for a full-scale VSENSE should be limited to 4.7 ms. To guarantee stable operation of the OUT buffer, an integration capacitance of 0.1 µF should be used for integration capacitor, CINT . The maximum integration period can be very long, limited by the leakage current and offset. A reset switch is configured internally to discharge the external integration capacitor, CINT. To enable the Coulomb Counting feature, SW_RST should be tied to either GND or COUT, allowing the 90 µs Monoshot Pulse to control the discharge of CINT. To close the reset switch and short out CINT, SW_RST may be tied high. TS1108’s Coulomb Counting interrupt is provided by the internal comparator with a push-pull output configuration. As shown in the block diagram, the integrator’s output is applied internally to the non-inverting terminal of the comparator, CIN+. Therefore the compara- tor’s output will latch high for 90 µs once the integrator’s output is charged to the voltage supplied to the comparator’s inverting terminal, CIN–. The inverting terminal of the comparator, CIN–, must be at a higher potential than the voltage supplied to VBIAS for proper oper- ation. The capacitive load at COUT should be minimized for minimal output delays. 2.5 VREF Divider The TS1108 provides an internal voltage divider network to set VBIAS and CIN–, eliminating the need for externally setting the required voltages. The VREF Divider is activated once the voltage applied to VREF is 0.9 V or greater. The VREF divider connects to VBIAS and CIN–, where the VBIAS voltage is equal to 50% of VREF while the CIN– voltage is equal to 90% of VREF . The VREF Divider exhibits a typical total series resistance of 4.6 MΩ from VREF to GND when activated. TS1108 Data Sheet System Overview silabs.com | Smart. Connected. Energy-friendly. Rev. 1.0 | 4 |
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