Connection Diagrams

Unit Loading/Fan Out

See Section 0 for U.L. definitions

54F/74F

Pin Names

Description

U.L.

Input I

HIGH/LOW

Output I

J

Data Inputs

1.0/1.0

20 µA/−0.6 mA

CP

Clock Pulse Inputs (Active Rising Edge)

1.0/1.0

20 µA/−0.6 mA

C

Direct Clear Inputs (Active LOW)

1.0/3.0

20 µA/−1.8 mA

S

Direct Set Inputs (Active LOW)

1.0/3.0

20 µA/−1.8 mA

Q

Outputs

50/33.3

−1 mA/20 mA

Truth Table

Inputs

Outputs

S

D

C

D

CP

J

K

QQ

LH

X

X

X

H

L

HL

X

X

X

L

H

LL

X

X

X

H

H

HH

N

ll

L

H

HH

N

h

l

Toggle

HH

N

lh

Q

0

Q

0

HH

N

hh

H

L

HH

L

X

X

Q

0

Q

0

H (h) = HIGH Voltage Level

L (l) = LOW Voltage Level

X = Immaterial

Lower case letters indicate the state of the referenced output one setup time prior to the LOW-to-HIGH clock transition.

Pin Assignment

for DIP, SOIC and Flatpak

DS009471-1

Pin Assignment

for LCC

DS009471-2

PrintDate=1997/08/28 PrintTime=11:45:23 10182 ds009471 Rev. No. 1

cmserv

Proof

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