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TPD3E001DRLRG4 데이터시트(PDF) 9 Page - Texas Instruments |
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TPD3E001DRLRG4 데이터시트(HTML) 9 Page - Texas Instruments |
9 / 22 page GND IO3 = VIA to GND IO1 IO2 GND 0.1µF IO1 IO2 IO3 VCC TPD3E001 www.ti.com SLLS683F – JULY 2006 – REVISED OCTOBER 2015 9 Power Supply Recommendations TPD3E001 is a passive TVS diode, so there is no requirement to power this device. However, for best IEC 61000-4-2 ESD performance and lowest capacitance performance, it is recommended that the VCC pin is biased with a 5V supply and that a 0.1µF capacitor is placed near the VCC pin. Take care to make sure that the maximum voltage specification for the VCC pin is not violated. 10 Layout 10.1 Layout Guidelines • The optimum placement is as close to the connector as possible. – EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures. – The PCB designer needs to minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces which are between the TVS and the connector. • Route the protected traces as straight as possible. • Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded corners with the largest radii possible. – Electric fields tend to build up on corners, increasing EMI coupling. 10.2 Layout Example Figure 5 is an example of how to layout three data lines with the TPD3E001. One example could be protecting a USB micro-AB connector from IEC ESD, as discussed in the Application and Implementation section. Figure 5. Routing with the DRL Package Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: TPD3E001 |
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