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SN74AUP1G74RSER 데이터시트(PDF) 3 Page - Texas Instruments |
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SN74AUP1G74RSER 데이터시트(HTML) 3 Page - Texas Instruments |
3 / 31 page PRE 1 7 2 6 8 3 5 4 VCC CLR Q GND CLK D Q GND CLK Q Q V CC CLR PRE 1 8 2 7 3 6 4 5 D1 D2 C1 C2 B1 B2 A1 A2 1 8 2 7 3 6 4 5 CLK D GND Q V Q CC PRE CLR 1 8 2 7 3 6 4 5 VCC CLK GND D Q PRE CLR Q SN74AUP1G74 www.ti.com SCES644D – MARCH 2006 – REVISED DECEMBER 2015 5 Pin Configuration and Functions DCU Package DQE Package 8-Pin VSSOP 8-Pin X2SON Top View Top View YFP or YZP Package RSE Package 8-Pin DSBGA 8-Pin UQFN Top View Top View Pin Functions(1) PIN I/O DESCRIPTION VSSOP, NAME UQFN DSBGA X2SON CLK 1 7 A1 I Rising edge triggered clock signal input CLR 6 2 C2 I Clear, Active low D 2 6 B1 I Data input GND 4 4 D1 — Ground PRE 7 1 B2 I Preset, Active low Q 5 3 D2 O Output Q 3 5 C1 O Inverted output VCC 8 8 A2 — Power supply (1) See Mechanical, Packaging, and Orderable Information for dimensions. Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: SN74AUP1G74 |
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