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SN74VMEH22501A-EP 데이터시트(PDF) 1 Page - Texas Instruments |
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SN74VMEH22501A-EP 데이터시트(HTML) 1 Page - Texas Instruments |
1 / 38 page 1D C1 CLK 1D C1 CLK 3B1 CLKAB LE CLKBA 3A1 To Seven Other Channels OE DIR 1OEAB 1OEBY 1A 1Y 2OEAB 2OEBY 2A 2Y 2B 1B 48 1 2 3 41 8 5 6 14 24 32 11 17 9 46 43 40 Product Folder Sample & Buy Technical Documents Tools & Software Support & Community SN74VMEH22501A-EP SCES625A – FEBRUARY 2005 – REVISED NOVEMBER 2015 SN74VMEH22501A-EP 8-Bit Universal Bus Transceiver and Two 1-Bit Bus Transceivers With Split LVTTL Port, Feedback Path, and 3-State Outputs 1 Features 2 Applications 1 • Controlled Baseline • Industrial Controls • Telecommunications – One Assembly/Test Site, One Fabrication Site • Instrumentation Systems • Enhanced Diminishing Manufacturing Sources (DMS) Support 3 Description • Enhanced Product-Change Notification The SN74VMEH22501A-EP 8-bit universal bus • Qualification Pedigree(1) transceiver has two integral 1-bit three-wire bus • Member of the Texas Instruments Widebus™ transceivers and is designed for 3.3-V VCC operation Family with 5-V tolerant inputs. The UBT transceiver allows • UBT™ Transceiver Combines D-Type Latches transparent, latched, and flip-flop modes of data transfer, and the separate LVTTL input and outputs and D-Type Flip-Flops for Operation in on the bus transceivers provide a feedback path for Transparent, Latched, or Clocked Modes control and diagnostics monitoring. This device • OEC™ Circuitry Improves Signal Integrity and provides a high-speed interface between cards Reduces Electromagnetic Interference (EMI) operating at LVTTL logic levels and VME64, VME64x, • Compliant With VME64, 2eVME, and 2eSST or VME320(2) backplane topologies. Protocols Validated at TA = –40°C to 85°C Device Information(3) • Bus Transceiver Split LVTTL Port Provides a PART NUMBER PACKAGE BODY SIZE (NOM) Feedback Path for Control and Diagnostics TSSOP (48) 4.40 mm × 9.70 mm Monitoring SN74VMEH22501A-EP TVSOP (48) 6.10 mm × 12.50 mm • I/O Interfaces are 5-V Tolerant (1) Component qualification in accordance with JEDEC and • B-Port Outputs (–48 mA/64 mA) industry standards to ensure reliable operation over an • Y and A-Port Outputs (–12 mA/12 mA) extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, • Ioff, Power-Up 3-State, and BIAS VCC Support Live temperature cycle, autoclave or unbiased HAST, Insertion electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as • Bus Hold on 3A-Port Data Inputs justifying use of this component beyond specified • 26- Ω Equivalent Series Resistor on 3A Ports and performance and environmental limits. Y Outputs (2) VME320 is a patented backplane construction by Arizona Digital, Inc. • Flow-Through Architecture Facilitates Printed (3) For all available packages, see the orderable addendum at Circuit Board Layout the end of the data sheet. • Distributed VCC and GND Pins Minimize High- Speed Switching Noise Logic Diagram (Positive Logic) • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) Pin numbers shown for DGG and DGV 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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