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74LVC1G175DBVRE4 데이터시트(PDF) 4 Page - Texas Instruments

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부품명 74LVC1G175DBVRE4
상세설명  Single D-Type Flip-Flop With Asynchronous Clear
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제조업체  TI1 [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI1 - Texas Instruments

74LVC1G175DBVRE4 데이터시트(HTML) 4 Page - Texas Instruments

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SN74LVC1G175
SCES560G – MARCH 2004 – REVISED JUNE 2015
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
VCC
Supply voltage
–0.5
6.5
V
VI
Input voltage
–0.5
6.5
V
VO
Voltage applied to any output in the high-impedance or power-off state(2)
–0.5
6.5
V
VO
Voltageapplied to any output in the high or low state(2)(3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
Continuous current through VCC or GND
±100
mA
Tstg
Storage temperature
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3)
The value of VCC is provided in the Recommended Operating Conditions table.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
2000
Electrostatic
V(ESD)
V
discharge
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
1000
(1)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2)
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
Operating
1.65
5.5
VCC
Supply voltage
V
Data retention only
1.5
VCC = 1.65 V to 1.95 V
0.65 × VCC
VCC = 2.3 V to 2.7 V
1.7
VIH
High-level input voltage
V
VCC = 3 V to 3.6 V
2
VCC = 4.5 V to 5.5 V
0.7 × VCC
VCC = 1.65 V to 1.95 V
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VIL
Low-level input voltage
V
VCC = 3 V to 3.6 V
0.8
VCC = 4.5 V to 5.5 V
0.3 × VCC
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
VCC = 1.65 V
–4
VCC = 2.3 V
–8
IOH
High-level output current
–16
mA
VCC = 3 V
–24
VCC = 4.5 V
–32
(1)
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
4
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Copyright © 2004–2015, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G175


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