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TS81001 데이터시트(PDF) 10 Page - Semtech Corporation

부품명 TS81001
상세설명  High Efficiency Receiver Controller for Wireless Power Systems
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TS81001
Final Datasheet
Rev 1.2
June 2, 2015
www.semtech.com
10 of 16
Semtech
Reset High Register (RESET_H)
Address:
0x07
Reset value:
0x00
7
6
5
4
3
2
1
0
RESET_KEY_H[7:0]
w
w
w
w
w
w
w
w
Bits 7:0 RESET_KEY_H[7:0]: Reset Key
0xAA: generate a system reset. Both the RESET_L and the RESET_H registers have to
be written with the correct key to generate a reset.
Any other value: a system reset is not generated.
Main Status Register (STATUS)
Address:
0x08
Reset value:
0xC0
7
6
5
4
3
2
1
0
CTS
CTS_API
Res
STATUS3
STATUS2
STATUS1
STATUS0
rw
rw
rw
rw
rw
rw
Bit 7
CTS: Clear To Send
This bit indicates if a new command can be issued to the controller.
0: The controller is busy processing a previous command. New commands should
not be sent to the controller.
1: The controller can accept a new command over the communication interface.
Bit 6
CTS_API: Clear to Send for API
This bit indicates if a new API call can be issued to the controller.
0: The controller is busy processing a previous API call. New API calls should not be
sent to the controller.
1: The controller can accept a new API call over the communication interface.
Bits 5:4 Reserved
Bit 3
STATUS3: STATUS3 Event Flag
0: No event is signaled in the STATUS3 register
1: An event is signaled in the STATUS3 register
Bit 2
STATUS2: STATUS2 Event Flag
0: No event is signaled in the STATUS2 register
1: An event is signaled in the STATUS2 register
Bit 1
STATUS1: STATUS1 Event Flag
0: No event is signaled in the STATUS1 register
1: An event is signaled in the STATUS1 register
Bit 0
STATUS0: STATUS0 Event Flag
0: No event is signaled in the STATUS0 register
1: An event is signaled in the STATUS0 register


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