TDA16888G datasheet(7/39 Pages) INFINEON

부품명	TDA16888G

상세설명	High Performance Power Combi Controller

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제조업체	INFINEON [Infineon Technologies AG]

홈페이지	http://www.infineon.com

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7 / 39 page

TDA 16888

Data Sheet

7

2000-02-28

Both PFC and PWM section are equipped with a peak current limitation, which is realized

by the comparators C3 and C9 sensing at pin 6 (PFC CL) and pin 11 (PWM CS)

respectively. When being activated this current limitation will immediately shut down the

respective gate drive PFC OUT (pin 8) or PWM OUT (pin 10).

Finally each pin is protected against electrostatic discharge.

Oscillator/Synchronization

The PFC and PWM clock signals as well as the PFC voltage ramp are synchronized by

the internal oscillator (see Figure 18). The oscillator’s frequency is set by an external

resistor connected to pin 16 (ROSC) and ground (see Figure 5). The corresponding

capacitor, however, is integrated to guarantee a low current consumption and a high

resistance against electromagnetic interferences. In order to ensure superior precision

of the clock frequency, the clock signal CLK OSC is derived from a triangular instead of

a saw-tooth signal. Furthermore to provide a clock reference CLK OUT with exactly 50%

duty cycle, the frequency of the oscillator’s clock signal CLK OSC is halved by a D-latch

before being fed into the PFC and PWM section respectively (see Figure 18).

The ramp signal of the PFC section

V

PFC RMP is composed of a slowly falling and a

steeply rising edge. This ramp has been reversed in contrast to the common practice, in

order to simultaneously allow for current measurement at pin 5 (GND S) and for external

compensation of OP2 by means of pin 5 (GND S) and pin 3 (PFC CC).

The oscillator can be synchronized with an external clock signal supplied at pin 12

(SYNC). However, since the oscillator’s frequency is halved before being fed into the

PFC and PWM section, a synchronization frequency being twice the operating frequency

is recommended. As long as the synchronization signal is H the oscillator’s triangular

signal

V

OSC is interrupted and its clock signal CLK OSC is H (see Figure 19 and

Figure 20). However, as soon as the external clock changes from H to L the oscillator is

released. Correspondingly, by means of an external clock signal supplied at pin 12

(SYNC) the oscillator frequency

f

OSC set by an external resistor at pin 16 (ROSC) can be

varied on principle only within the range from 0.66

f

OSC to 2 fOSC. If the oscillator has to

be synchronized over a wider frequency range, a synchronization by means of the sink

current at pin 16 (ROSC) has to be preferred to a synchronization by means of pin 12

(SYNC). Anyhow, please note, that pin 12 (SYNC) is not meant to permanently

shutdown both PFC and PWM section. It can be used to halt the oscillator freezing the

prevailing state of both drivers but does not allow to automatically shut them down. A

shutdown can be achieved by shorting pin 2 (

V

REF) to ground, instead.

Finally, In order to reduce the overall current consumption under low load conditions, the

oscillator frequency itself is halved as long as the voltage at pin 13 (PWM SS) is less

than 0.4 V (disabled PWM section).

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TDA16888G 데이터시트(PDF) 7 Page - Infineon Technologies AG

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