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AD6679 데이터시트(PDF) 10 Page - Analog Devices |
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AD6679 데이터시트(HTML) 10 Page - Analog Devices |
10 / 81 page AD6679 Data Sheet Rev. B | Page 10 of 81 D13 D0 D13 D0 CLK+ DCO± (DATA CLOCK OUTPUT) 0° PHASE ADJUST DCO± ((DATA CLOCK OUTPUT) 90° PHASE ADJUST1 DCO± (DATA CLOCK OUTPUT) 180° PHASE ADJUST DCO± (DATA CLOCK OUTPUT) 270° PHASE ADJUST2 SYNC+ APERTURE DELAY N N + x N – 1 N + y N + 33 N + 34 N + 35 N + 36 SYNCHRONOUS LOW TO HIGH TRANSITION OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF THE CLK SIGNAL CAUSES THE DCO INTERNAL DIVIDER TO BE RESET D0± D13± FIXED DELAY FROM SYNC EVENT TO DCO KNOWN PHASE CONVERTER 0 SAMPLE [N] N + 37 N + 38 N + 39 VIN±x 190° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±. 2270° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±. OVR OVR D13 D0 OVR D13 D0 OVR D13 D0 OVR D13 D0 OVR D13 D0 OVR CLK– SYNC– OVR+ (OVERRANGE/STATUS BIT) OVR– tCLK tCH tDCO 2 × tCLK tPD tSKEWR CONVERTER 0 SAMPLE [N + 1] CONVERTER 0 SAMPLE [N + 2] CONVERTER 0 SAMPLE [N + 3] CONVERTER 0 SAMPLE [N + 4] STATUS BIT SELECTED BY OUTPUT MODE CONTROL 1 BITS, REGISTER 0x559[2:0] IN THE REGISTER MAP tSKEWF Figure 4. Parallel Interleaved Mode—One Virtual Converter (Decimate by 1) |
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