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AD6674BCPZ-1000 데이터시트(PDF) 1 Page - Analog Devices

부품명 AD6674BCPZ-1000
상세설명  385 MHz BW IF Diversity Receiver
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홈페이지  http://www.analog.com
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AD6674BCPZ-1000 데이터시트(HTML) 1 Page - Analog Devices

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385 MHz BW IF Diversity Receiver
Data Sheet
AD6674
FEATURES
JESD204B (Subclass 1) coded serial digital outputs
In band SFDR = 83 dBFS at 340 MHz (750 MSPS)
In band SNR = 66.7 dBFS at 340 MHz (750 MSPS)
1.4 W total power per channel at 750 MSPS (default settings)
Noise density = −153 dBFS/Hz at 750 MSPS
1.25 V, 2.5 V, and 3.3 V dc supply operation
Flexible input range
AD6674-750 and AD6674-1000
1.46 V p-p to 1.94 V p-p (1.70 V p-p nominal)
AD6674-500
1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal)
95 dB channel isolation/crosstalk
Amplitude detect bits for efficient automatic gain control
(AGC) implementation
Noise shaping requantizer (NSR) option for main receiver
function
Variable dynamic range (VDR) option for digital
predistortion (DPD) function
2 integrated wideband digital processors per channel
12-bit numerically controlled oscillator (NCO), up to
4 cascaded half-band filters
Differential clock inputs
Integer clock divide by 1, 2, 4, or 8
Energy saving power-down modes
Flexible JESD204B lane configurations
Small signal dither
APPLICATIONS
Diversity multiband, multimode digital receivers
3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A
DOCSIS 3.0 CMTS upstream receive paths
HFC digital reverse path receivers
GENERAL DESCRIPTION
The AD6674 is a 385 MHz bandwidth mixed-signal
intermediate frequency (IF) receiver. It consists of two, 14-bit
1.0 GSPS/750 MSPS/500 MSPS analog-to-digital converters
(ADC) and various digital signal processing blocks consisting of
four wideband DDCs, an NSR, and VDR monitoring. It has an
on-chip buffer and a sample-and-hold circuit designed for low
power, small size, and ease of use. This product is designed to
support communications applications capable of sampling wide
bandwidth analog signals of up to 2 GHz. The AD6674 is
optimized for wide input bandwidth, high sampling rate,
excellent linearity, and low power in a small package.
The dual ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth inputs supporting a variety of
user-selectable input ranges. An integrated voltage reference
eases design considerations.
FUNCTIONAL BLOCK DIAGRAM
VIN+A
VIN–A
VIN+B
VIN–B
AD6674
SERDOUT0±
SERDOUT1±
SERDOUT2±
SERDOUT3±
SYSREF±
PDWN/
STBY
SYNCINB±
FD_A
FD_B
BUFFER
BUFFER
JESD204B
SUBCLASS 1
CONTROL
FAST
DETECT
SIGNAL
MONITOR
V_1P0
AGND
DRGND
DGND
SDIO SCLK CSB
AVDD1
(1.25V)
AVDD2
(2.5V)
AVDD3
(3.3V)
AVDD1_SR
(1.25V)
DVDD
(1.25V)
DRVDD
(1.25V)
SPIVDD
(1.8V TO 3.3V)
4
SIGNAL
MONITOR
ADC
ADC
SPI CONTROL
CLK+
CLK–
÷2
÷4
CLOCK
GENERATION
÷8
SIGNAL PROCESSING
DIGITAL DOWN CONVERSION
(×4)
DIGITAL DOWN CONVERSION
(×4)
DIGITAL DOWN CONVERSION
(×4)
DIGITAL DOWNCONVERSION
(×4)
NOISE SHAPING REQUANTIZER
(×2)
NOISE SHAPING REQUANTIZER
(×2)
VARIABLE DYNAMIC RANGE
(×2)
VARIABLE DYNAMIC RANGE
(×2)
Figure 1.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2014–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com


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