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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AD9993BBCZ 데이터시트(PDF) 9 Page - Analog Devices |
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AD9993BBCZ 데이터시트(HTML) 9 Page - Analog Devices |
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9 / 56 page  Data Sheet AD9993 Rev. A | Page 9 of 56 Pin No. Mnemonic Description A11 A_VINP ADC A Voltage Input Positive. A13 IBIAS_TEST Test. Connect to ground. B1 CLKN External Master Clock Input Negative B2 REFCLK On-Chip PLL Synthesizer Reference Clock Input. B4 D_VINN ADC D Input Voltage Negative. B5 D_CML Common-Mode Level Bias Voltage Output ADC D. B6 C_VINN ADC C Input Voltage Negative. B9 B_VINN ADC B Voltage Input Negative. B10 A_CML Common-Mode Level Bias Voltage Output for ADC A. B11 A_VINN ADC A Voltage Input Negative. B13 IOUTA_N DAC A Output Current Negative. B14 IOUTA_P DAC A Output Current Positive. C13, C14, F5 AVDD33 3.3 V Analog Power Supply. D1 LDO15 On-Chip Regulator Output. Bypass with 4.7 μF capacitor to ground. D2 CP Connection for On-Chip PLL Optional External Portion of Loop Filter. D13 IOUTB_N DAC B Output Current Negative. D14 IOUTB_P DAC B Output Current Positive. E1, E2, E3, E4, E5, E6, E7, E8, E9, E10, E11, E12, E13, E14, G12 AVDD 1.8 V Analog Power Supply. F1 PDWN Power-Down. Set to 1 to place the device in low power mode. F2 ALERT Active Low Alarm Indicator Output, Open Drain. F3 RST Reset Input, Active Low. F4 MODE Connect to ground. F12 VREF_DAC DAC A and DAC B Reference Voltage Input/Output. F13 FSAJ_B DAC B Full-Scale Current Output Adjust. F14 FSAJ_A DAC A Full-Scale Current Output Adjust. G1 SPI_SCLK SPI Clock. G2 SPI_CS SPI Chip Select, Active Low. G3 SPI_SDI SPI Serial Data Input. G4 SPI_SDO SPI Serial Data Output. G5, J1, J2, J3, J4, J5, J6, J7, J8, J9, J10, J11, J12, J13, J14 DVDD 1.8 V Digital Supply. G13 CML_B DAC B Common-Mode Control. Connect to ground for DAC bias < 0.5 V. Connect a 0.1 μF capacitor between CML_B and ground for other DAC bias values ≥ 0.5 V. G14 CML_A DAC A Common-Mode Control. Connect to ground for DAC bias < 0.5 V. Connect a 0.1 μF capacitor between CML_A and ground for other DAC bias values ≥ 0.5 V. H1, H2, H3, H4, H5, H6, H7, H8, H9, H10, H11, H12, H13, H14, N7, N8, P1, P14 DVSS Digital Ground. K1 DIN6B_N DAC B Data Input Lane 6 Negative. K2 DIN4B_N DAC B Data Input Lane 4 Negative. K3 DIN1B_N DAC B Data Input Lane 1 Negative. K4 DOUT3D_P ADC D Data Output Lane 3 Positive. K5 DOUT3D_N ADC D Data Output Lane 3 Negative. K6 DOUT3C_P ADC C Data Output Lane 3 Positive. K7 DCO_N LVDS Data Clock Output Negative. K8 DCO_P LVDS Data Clock Output Positive. K9 DOUT3B_P ADC B Data Output Lane 3 Positive. K10 DOUT3A_N ADC A Data Output Lane 3 Negative. K11 DOUT3A_P ADC A Data Output Lane 3 Positive. K12 DIN1A_N DAC A Data Input Lane 1 Negative. K13 DIN4A_N DAC A Data Input Lane 4 Negative. K14 DIN6A_N DAC A Data Input Lane 6 Negative. |
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