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LMZ34202RVQT 데이터시트(PDF) 7 Page - Texas Instruments |
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LMZ34202RVQT 데이터시트(HTML) 7 Page - Texas Instruments |
7 / 31 page 7 LMZ34202 www.ti.com SNVSAJ2 – MARCH 2016 Product Folder Links: LMZ34202 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Electrical Characteristics (continued) Over -40°C to +105°C free-air temperature, PVIN = 24 V, VOUT = 5 V, IOUT = IOUT max, ƒsw = 500 kHz, CIN1 = 1 x 10-µF, 100-V 1210 ceramic, CIN2 = 1 x 100-µF 100-V electrolytic bulk, and COUT = 3 x 47-µF, 16-V 1210 ceramic (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (4) The specified minimum ceramic input capacitance represents the standard capacitance value. The actual effective capacitance after considering the effects of DC bias and temperature variation should be ≥ 4.7 µF. (5) The amount of required output capacitance varies depending on the output voltage (see Output Capacitor Selection). The minimum required output capacitance must be comprised of ceramic capacitance. The amount of required ceramic capacitance represents the standard capacitance value. Locate the capacitance close to the device. Adding additional ceramic or non-ceramic capacitance close to the load improves the response of the regulator to load transients. (6) The maximum allowable output capacitance varies depending on the output voltage (see Output Capacitor Selection). THERMAL SHUTDOWN TSHUTDOWN Thermal shutdown Shutdown Temperature 160 °C Hysteresis 10 °C INPUT/OUTPUT CAPACITANCE CIN External input capacitance ceramic 10(4) µF non-ceramic 100 µF COUT External output capacitance Ceramic 64(5) See(6) µF Non-ceramic 100 See(6) µF ceramic + non-ceramic See(6) µF Equivalent series resistance (ESR) 20 m Ω 6.6 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ƒSW Switching frequency RT and RTSEL pins open 410 500 590 kHz ƒCLK CLK Control Synchronization frequency 200 1000 kHz VCLK-H CLK high level 2 5.5 V VCLK-L CLK low level 0.4 V DCLK CLK duty cycle 10% 50% 90% |
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