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ADC0820CCWM 데이터시트(PDF) 5 Page - National Semiconductor (TI) |
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ADC0820CCWM 데이터시트(HTML) 5 Page - National Semiconductor (TI) |
5 / 22 page AC Electrical Characteristics (Continued) The following specifications apply for V CC=5V, tr=tf=20 ns, VREF(+)=5V, VREF(−)=0V and TA=25˚C unless otherwise speci- fied. Typ Tested Design Parameter Conditions (Note 6) Limit Limit Units (Note 7) (Note 8) t ACC2, Access Time (Delay from Falling Edge of RD to Output Valid) Pin 7 = V CC,tRD>tI; Figure 4 C L=15 pF 70 120 ns C L=100 pF 90 150 ns t ACC3, Access Time (Delay from Rising Edge of RDY to Output Valid) R PULLUP = 1k and CL = 15 pF 30 ns t I, Internal Comparison Time Pin 7=V CC; Figures 4, 5 800 1300 ns C L=50 pF t 1H,t0H, TRI-STATE Control R L=1k, CL=10 pF 100 200 ns (Delay from Rising Edge of RD to Hi-Z State) t INTL, Delay from Rising Edge of Pin 7 = V CC,CL= 50 pF WR to Falling Edge of INT t RD>tI; Figure 4 t I ns t RD<tI; Figure 3 t RD+200 t RD+290 ns t INTH, Delay from Rising Edge of Figures 2, 3, 4 125 225 ns RD to Rising Edge of INT C L=50 pFc t INTHWR, Delay from Rising Edge of Figure 5,C L=50 pF 175 270 ns WR to Rising Edge of INT t RDY, Delay from CS to RDY Figure 2,C L=50 pF, Pin 7 =0 50 100 ns t ID, Delay from INT to Output Valid Figure 5 20 50 ns t RI, Delay from RD to INT Pin 7=V CC,tRD<tI 200 290 ns Figure 3 t P, Delay from End of Conversion Figures 2, 3, 4, 5 500 ns to Next Conversion (Note 4) See Graph Slew Rate, Tracking 0.1 V/µs C VIN, Analog Input Capacitance 45 pF C OUT, Logic Output Capacitance 5 pF C IN, Logic Input Capacitance 5 pF Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. Note 2: All voltages are measured with respect to the GND pin, unless otherwise specified. Note 3: Total unadjusted error includes offset, full-scale, and linearity errors. Note 4: Accuracy may degrade if tWR or tRD is shorter than the minimum value specified. See Accuracy vs tWR and Accuracy vs tRD graphs. Note 5: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V −or V IN > V +) the absolute value of current at that pin should be limited to 1 mA or less. The 4 mA package input current limits the number of pins that can exceed the power supply boundaries witha1mA current limit to four. Note 6: Typicals are at 25˚C and represent most likely parametric norm. Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 8: Design limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels. Note 9: Human body model, 100 pF discharaged through a 1.5 k Ω resistor. www.national.com 5 |
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