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SM320VC33GNMM150 데이터시트(PDF) 5 Page - Texas Instruments |
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SM320VC33GNMM150 데이터시트(HTML) 5 Page - Texas Instruments |
5 / 53 page SM320VC33, SMJ320VC33 www.ti.com SGUS034F – FEBRUARY 2001 – REVISED JUNE 2015 Pin Functions PIN CONDITIONS WHEN TYPE(1) DESCRIPTION SIGNAL IS Z TYPE(2) NAME QTY PRIMARY-BUS INTERFACE D31- D0 32 I/O/Z 32-bit data port S H R Data port bus keepers. (See Figure 30) S A23- A0 24 O/Z 24-bit address port S H R R/W 1 O/Z Read/write. R/W is high when a read is performed and low when a write is S H R performed over the parallel interface. STRB 1 O/Z Strobe. For all external-accesses S H PAGE0 to 1 O/Z Page strobes. Four decoded page strobes for external access S H R PAGE3 RDY 1 I Ready. RDY indicates that the external device is prepared for a transaction completion. HOLD 1 I Hold. When HOLD is a logic low, any ongoing transaction is completed. A23 to A0, D31 to D0, STRB, and R/W are placed in the high-impedance state and all transactions over the primary-bus interface are held until HOLD becomes a logic high or until the NOHOLD bit of the primary-bus-control register is set. HOLDA 1 O/Z Hold acknowledge. HOLDA is generated in response to a logic-low on HOLD. S HOLDA indicates that A23 to A0, D31 to D0, STRB, and R/W are in the high- impedance state and that all transactions over the bus are held. HOLDA is high in response to a logic-high of HOLD or the NOHOLD bit of the primary-bus-control register is set. CONTROL SIGNALS RESET 1 I Reset. When RESET is a logic low, the device is in the reset condition. When RESET becomes a logic high, execution begins from the location specified by the reset vector. EDGEMO 1 I Edge mode. Enables interrupt edge mode detection. DE INT3 to 4 I External interrupts INT0 IACK 1 O/Z Internal acknowledge. IACK is generated by the IACK instruction. IACK can be S used to indicate when a section of code is being executed. MCBL/MP 1 I Microcomputer bootloader/microprocessor mode-select SHZ 1 I Shutdown high impedance. When active, SHZ places all pins in the high- impedance state. SHZ can be used for board-level testing or to ensure that no dual-drive conditions occur. CAUTION: A low on SHZ corrupts the device memory and register contents. Reset the device with SHZ high to restore it to a known operating condition. XF1, XF0 2 I/O/Z External flags. XF1 and XF0 are used as general-purpose I/Os or to support S R interlocked processor instruction. SERIAL PORT 0 SIGNALS CLKR0 1 I/O/Z Serial port 0 receive clock. CLKR0 is the serial shift clock for the serial port 0 S R receiver. CLKX0 1 I/O/Z Serial port 0 transmit clock. CLKX0 is the serial shift clock for the serial port 0 S R transmitter. DR0 1 I/O/Z Data-receive. Serial port 0 receives serial data on DR0. S R DX0 1 I/O/Z Data-transmit output. Serial port 0 transmits serial data on DX0. S R FSR0 1 I/O/Z Frame-synchronization pulse for receive. The FSR0 pulse initiates the data- S R receive process using DR0. FSX0 1 I/O/Z Frame-synchronization pulse for transmit. The FSX0 pulse initiates the data- S R transmit process using DX0. TIMER SIGNALS TCLK0 1 I/O/Z Timer clock 0. As an input, TCLK0 is used by timer 0 to count external pulses. As S R an output, TCLK0 outputs pulses generated by timer 0. (1) I = input, O = output, Z = high-impedance state (2) S = SHZ active, H = HOLD active, R = RESET active Copyright © 2001–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: SM320VC33 SMJ320VC33 |
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