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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ADM1260ACPZ-RL7 데이터시트(PDF) 1 Page - Analog Devices |
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ADM1260ACPZ-RL7 데이터시트(HTML) 1 Page - Analog Devices |
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1 / 71 page  Super Sequencer with Interchip Bus and Nonvolatile Fault Recording Data Sheet ADM1260 Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES Complete supervisory and sequencing solution for up to 10 supplies per device Interchip bus (ICB) simplifies multidevice connections and sequencing system operation Supports up to 4 devices 16 event deep black box nonvolatile fault recording 10 supply fault detectors enable supervision of supplies <0.5% accuracy at all voltages at 25°C <1.0% accuracy across all voltages and temperatures 5 selectable input attenuators allow supervision of supplies 14.4 V on VH and 6.0 V on VP1 to VP4 (VPx) 5 dual function inputs: VX1 to VX5 (VXx) High impedance input to supply fault detector with thresholds between 0.573 V and 1.375 V General-purpose logic input 10 programmable driver outputs: PDO1 to PDO10 (PDOx) Open-collector with an external pull-up resistor Push/pull output, driven to VDDCAP or VPx Open-collector with weak pull-up to VDDCAP or VPx Internally charge pumped high drive for use with external N-FET (PDO1 to PDO6 only) Sequencing engine (SE) implements state machine control of the PDOx outputs State changes conditional on input events Enables complex control of boards Power-up and power-down sequence control Fault event handling Interrupt generation on warnings Watchdog function can be integrated in the SE Program software control of sequencing through the SMBus Complete voltage margining solution for 6 voltage rails 6 output voltage 8-bit DACs (0.300 V to 1.552 V) allow voltage adjustment via dc-to-dc converter trim/feedback node 12-bit ADC for readback of all supervised voltages Reference input (REFIN) with two input options Driven directly from the 2.048 V (±0.25%) REFOUT pin External reference for improved ADC performance Powered by the highest voltage on either VPx or VH Voltage on VPx or VH must be greater than the undervoltage lockout (UVLO) threshold Electronically erasable programmable read-only memory (EEPROM) Industry-standard, 2-wire bus interface (SMBus) PDOx pins guaranteed low with VH and VPx = 1.2 V Available in a 40-lead, 6 mm × 6 mm LFCSP package FUNCTIONAL BLOCK DIAGRAM PDO7 PDO8 PDO9 PDO10 PDOGND VDDCAP VDD ARBITRATOR DAC1 VOUT DAC DAC2 VOUT DAC DAC3 VOUT DAC DAC4 VOUT DAC DAC5 VOUT DAC DAC6 VOUT DAC GND VCCP VX1 VX2 VX3 VX4 VX5 VP1 VP2 VP3 VP4 VH AGND PROGRAMMABLE RESET GENERATORS (SFDs) DUAL- FUNCTION INPUTS (LOGIC INPUTS OR SFDs) SEQUENCING ENGINE CONFIGURABLE OUTPUT DRIVERS (LV CAPABLE OF DRIVING LOGIC SIGNALS) PDO1 PDO2 PDO3 PDO4 PDO5 PDO6 SDA SCL A1 A0 SMBus INTERFACE CDA REFIN CCL INTERCHIP BUS REFGND REFOUT VREF FAULT RECORDING 12-BIT SAR ADC EEPROM CLOSED-LOOP MARGINING SYSTEM ADM1260 CONFIGURABLE OUTPUT DRIVERS (HV CAPABLE OF DRIVING GATES OF N-FET) Figure 1. APPLICATIONS Central office systems Servers/routers Multivoltage system line cards Digital signal processor (DSP)/field programmable gate array (FPGA) supply sequencing In-circuit testing of margined supplies |
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