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AD7656ABSTZ-RL 데이터시트(PDF) 9 Page - Analog Devices

부품명 AD7656ABSTZ-RL
상세설명  250 kSPS, 6-Channel, Simultaneous Sampling, Bipolar 16-Bit ADC
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Data Sheet
AD7656A
Pin No.
Mnemonic
Description
27
RANGE
Analog Input Range Selection. Logic input. The logic level on this pin determines the input range
of the analog input channels. When this pin is Logic 1 at the falling edge of BUSY, the range for the
next conversion is ±2 × VREF. When this pin is Logic 0 at the falling edge of BUSY, the range for the
next conversion is ±4 × VREF. In hardware select mode, the RANGE pin is checked on the falling edge
of BUSY. In software mode (H/S SEL = 1), the RANGE pin can be tied to DGND, and the input range is
determined by the RNGA, RNGB, and RNGC bits in the control register.
28
RESET
Reset Input. When set to logic high, this pin resets the AD7656A, and the current conversion, if
any, is aborted. The internal register is set to all 0s. In hardware mode, the AD7656A is configured
depending on the logic levels on the hardware select pins. In all modes, after power-up, the device
must receive a RESET pulse. The reset high pulse is typically 100 ns wide. After the RESET pulse, the
AD7656A needs to see a valid CONVST pulse to initiate a conversion; this typically consists of a high-
to-low CONVST edge followed by a low-to-high CONVST edge. During the RESET pulse, the CONVST x
signal must be high.
29
W/B
Word/Byte Input. When this pin is logic low, data can be transferred to and from the AD7656A using
the parallel data lines DB15 to DB0. When this pin is logic high, byte mode is enabled. In this mode,
data is transferred using data lines DB15 to DB8 and DB7 takes on its HBEN function. To obtain the
16-bit conversion result, 2-byte reads are required. In serial mode, tie this pin to DGND.
30
VSS
Negative Power Supply Voltage. This is the negative supply voltage for the analog input section. Place
10 µF and 100 nF decoupling capacitors on the VSS pin.
31
VDD
Positive Power Supply Voltage. This is the positive supply voltage for the analog input section. Place
10 µF and 100 nF decoupling capacitors on the VDD pin.
32, 37, 38, 43,
44, 49, 52, 53,
55, 57, 59
AGND
Analog Ground. Ground reference point for all analog circuitry on the AD7656A. Refer all analog input
signals and any external reference signal to the AGND voltage. Connect all AGND pins to the AGND
plane of a system. Ideally, the AGND and DGND voltages are at the same potential and must not be
more than 0.3 V apart, even on a transient basis.
33, 36, 39,
42, 45, 48
V1 to V6
Analog Input 1 to Analog Input 6. These are six single-ended analog inputs. In hardware mode,
the analog input range on these channels is determined by the RANGE pin. In software mode, it
is determined by Bit RNGC to Bit RNGA of the control register (see Table 9).
34, 35, 40,
41, 46, 47,
50, 60
AVCC
Analog Supply Voltage, 4.75 V to 5.25 V. The AVCC pin is the supply voltage for the ADC cores. Ideally,
the AVCC and DVCC voltages are at the same potential and must not be more than 0.3 V apart, even
on a transient basis. Decouple these supply pins to AGND, and place 10 µF and 100 nF decoupling
capacitors on the AVCC pins.
51
REFIN/REFOUT
Reference Input/Reference Output. The on-chip reference is available on Pin 51 for external use to
the AD7656A. Alternatively, the internal reference can be disabled and an external reference can be
applied to this input. See the Reference Section. When the internal reference is enabled, decouple
Pin 51 using at least a 10 µF decoupling capacitor.
54, 56, 58
REFCAPA, REFCAPB,
REFCAPC
Reference Capacitor A, Reference Capacitor B, and Reference Capacitor C. Decoupling capacitors are
connected to these pins, which decouples the reference buffer for each ADC pair. Decouple each
REFCAPx pin to AGND using 10 µF and 100 nF capacitors.
61
SER/PAR/SEL
Serial/Parallel Selection Input. When this pin is low, the parallel interface is selected. When this pin is
high, the serial interface mode is selected. In serial mode, DB10 to DB8 take on their DOUT C to
DOUT A function, DB0 to DB2 take on their DOUT select function, and DB7 takes on its DCEN
function. In serial mode, tie DB15 and DB13 to DB11 to DGND
62
H/S SEL
Hardware/Software Select Input. Logic input. When H/S SEL = 0, the AD7656A operates in hardware
select mode, and the ADC pairs to be simultaneously sampled are selected by the CONVST x pins.
When H/S SEL = 1, the ADC pairs to be sampled simultaneously are selected by writing to the
control register. In serial mode, CONVST A is used to initiate conversions on the selected ADC pairs.
63
WR/REFEN/DIS
Write Data/Reference Enable/Disable. When H/S SEL pin is high and both CS and WR are logic low,
DB15 to DB8 are used to write data to the internal control register. When the H/S SEL pin is low, this
pin is used to enable or disable the internal reference. When H/S SEL = 0 and REFEN/DIS = 0, the internal
reference is disabled, and an external reference must be applied to the REFIN/REFOUT pin. When
H/S SEL = 0 and REFEN/DIS = 1, the internal reference is enabled and the REFIN/REFOUT pin must be
decoupled. See the Reference Section.
1
Multifunction pin names may be referenced by their relevant function only.
Rev. 0 | Page 9 of 28


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