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AD7770 데이터시트(PDF) 7 Page - Analog Devices |
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AD7770 데이터시트(HTML) 7 Page - Analog Devices |
7 / 94 page Data Sheet AD7770 Rev. A | Page 7 of 94 Parameter Test Conditions/Comments Min Typ Max Unit Offset Matching 25 µV Gain Error ±0.1 % FS Gain Drift vs. Temperature ±0.75 ppm/°C Gain Matching ±0.1 % SAR ADC Speed and Performance Resolution 12 Bits Analog Input Range AVSS4 + 0.1 AVDD4 − 0.1 V Analog Input Common-Mode Range AVSS4 + 0.1 (AVDD4 + AVSS4)/2 AVDD4 − 0.1 V Analog Input Dynamic Current 256 kSPS, 0 dBFS ±100 nA Throughput 256 kSPS DC Accuracy Differential mode INL 1.5 LSB DNL No missing codes (12-bit) −0.99 +1 LSB Offset ±1 LSB Gain 12 LSB AC Performance SNR 1 kHz 66 dB THD 1 kHz −81 dB VCM PIN Output (AVDD1x + AVSSx)/2 V Load Current, IL 1 mA Load Regulation, ∆VOUT/∆IL 12 mV/mA Short-Circuit Current 5 mA LOGIC INPUTS Input Voltage High, VIH 0.7 × IOVDD V Low, VIL 0.4 V Hysteresis 0.1 V Input Currents −10 +10 µA LOGIC OUTPUTS3 Output Voltage High, VOH IOVDD ≥ 3 V, ISOURCE = 1 mA 0.8 × IOVDD V 2.3 V ≤ IOVDD < 3 V, ISOURCE = 500 μA 0.8 × IOVDD V IOVDD < 2.3 V, ISOURCE = 200 μA 0.8 × IOVDD V Low, VOL IOVDD ≥ 3 V, ISINK = 2 mA 0.4 V 2.3 V ≤ IOVDD < 3 V, ISINK = 1 mA 0.4 V IOVDD < 2.3 V, ISINK = 100 μA 0.4 V Leakage Current Floating state −10 +10 µA Output Capacitance Floating state 10 pF Σ-Δ ADC Data Output Coding Twos complement SAR ADC Data Output Coding Binary |
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