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CLC005 데이터시트(PDF) 4 Page - National Semiconductor (TI) |
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CLC005 데이터시트(HTML) 4 Page - National Semiconductor (TI) |
4 / 12 page Operation INPUT INTERFACING The CLC005 has high impedance, emitter-follower buffered, differential inputs. Single-ended signals may also be input. Transmission lines supplying input signals must be properly terminated close to the CLC005. Either A.C. or D.C. coupling as in Figure 2 or Figure 3 may be used. Figures 2, 4 and Fig- ure 5 show how Thevenin-equivalent resistor networks are used to provide input termination and biasing. The input D.C. common-mode voltage range is 0.8V to 2.5V below the posi- tive power supply (V CC). Input signals plus bias should be kept within the specified common-mode range. For an 800 mV P-P input signal, typical input bias levels range from 1.2V to 2.1V below the positive supply. Load Type Resistor to V CC (R1) Resistor to V EE (R2) ECL, 50 Ω, 5V, V T=2V 82.5 Ω 124 Ω ECL, 50 Ω, 5.2V, V T=2V 80.6 Ω 133 Ω ECL, 75 Ω, 5V, V T=2V 124 Ω 187 Ω ECL, 75 Ω, 5.2V, V T=2V 121 Ω 196 Ω 800mV P-P,50Ω, 5V, VT=1.6V 75.0 Ω 154 Ω 800mV P-P,75Ω, 5V, VT=1.6V 110 Ω 232 Ω 800mV P-P, 2.2KΩ, 5V, VT=1.6V 3240 Ω 6810 Ω DS100144-4 FIGURE 1. Input Stage DS100144-5 FIGURE 2. AC Coupled Input www.national.com 4 |
유사한 부품 번호 - CLC005 |
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유사한 설명 - CLC005 |
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