전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

SST39SF020-70-4C-W 데이터시트(PDF) 2 Page - Silicon Storage Technology, Inc

부품명 SST39SF020-70-4C-W
상세설명  2 Megabit (256K x 8) Multi-Purpose Flash
Download  23 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  SST [Silicon Storage Technology, Inc]
홈페이지  http://www.sst.com/
Logo SST - Silicon Storage Technology, Inc

SST39SF020-70-4C-W 데이터시트(HTML) 2 Page - Silicon Storage Technology, Inc

  SST39SF020-70-4C-W Datasheet HTML 1Page - Silicon Storage Technology, Inc SST39SF020-70-4C-W Datasheet HTML 2Page - Silicon Storage Technology, Inc SST39SF020-70-4C-W Datasheet HTML 3Page - Silicon Storage Technology, Inc SST39SF020-70-4C-W Datasheet HTML 4Page - Silicon Storage Technology, Inc SST39SF020-70-4C-W Datasheet HTML 5Page - Silicon Storage Technology, Inc SST39SF020-70-4C-W Datasheet HTML 6Page - Silicon Storage Technology, Inc SST39SF020-70-4C-W Datasheet HTML 7Page - Silicon Storage Technology, Inc SST39SF020-70-4C-W Datasheet HTML 8Page - Silicon Storage Technology, Inc SST39SF020-70-4C-W Datasheet HTML 9Page - Silicon Storage Technology, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 2 / 23 page
background image
2
© 1998 Silicon Storage Technology, Inc.
326-10 12/98
2 Megabit Multi-Purpose Flash
SST39SF020
Preliminary Specifications
keeping CE# low. The address bus is latched on the
falling edge of WE# or CE#, whichever occurs last. The
data bus is latched on the rising edge of WE# or CE#,
whichever occurs first.
Read
The Read operation of the SST39SF020 device is con-
trolled by CE# and OE#, both have to be low for the
system to obtain data from the outputs. CE# is used for
device selection. When CE# is high, the chip is dese-
lected and only standby power is consumed. OE# is the
output control and is used to gate data from the output
pins. The data bus is in high impedance state when either
CE# or OE# is high. Refer to the Read cycle timing
diagram for further details (Figure 3).
Byte Program Operation
The SST39SF020 device is programmed on a byte-by-
byte basis. The Program operation consists of three
steps. The first step is the three-byte-load sequence for
Software Data Protection. The second step is to load
byte address and byte data. During the Byte Program
operation, the addresses are latched on the falling edge
of either CE# or WE#, whichever occurs last. The data is
latched on the rising edge of either CE# or WE#, which-
ever occurs first. The third step is the internal Program
operation which is initiated after the rising edge of the
fourth WE# or CE#, whichever occurs first. The Program
operation, once initiated, will be completed, within 30 µs.
See Figures 4 and 5 for WE# and CE# controlled
Program operation timing diagrams and Figure 14 for
flowcharts. During the Program operation, the only valid
reads are Data# Polling and Toggle Bit. During the
internal Program operation, the host is free to perform
additional tasks. Any commands written during the inter-
nal Program operation will be ignored.
Sector Erase Operation
The Sector Erase operation allows the system to erase
the device on a sector by sector basis. The sector
architecture is based on uniform sector size of 4 KByte.
The Sector Erase operation is initiated by executing a
six-byte-command load sequence for software data pro-
tection with sector erase command (30H) and sector
address (SA) in the last bus cycle. The address lines
A12-A17 will be used to determine the sector address.
The sector address is latched on the falling edge of the
sixth WE# pulse , while the command (30H) is latched on
the rising edge of the sixth WE# pulse. The internal Erase
operation begins after the sixth WE# pulse. The end of
Erase can be determined using either Data# Polling or
Toggle Bit methods. See Figure 8 for timing waveforms.
Any commands written during the Sector Erase opera-
tion will be ignored.
Chip-Erase Operation
The SST39SF020 device provides a Chip-Erase opera-
tion, which allows the user to erase the entire memory
array to the “1’s” state. This is useful when the entire
device must be quickly erased.
The Chip Erase operation is initiated by executing a six-
byte software data protection command sequence with
Chip Erase command (10H) with address 5555H in the
last byte sequence. The Erase operation begins with the
rising edge of the sixth WE# or CE#, whichever occurs
first. During the Erase operation, the only valid read is
Toggle Bit or Data# Polling. See Table 4 for the command
sequence, Figure 9 for timing diagram, and Figure 17 for
the flowchart. Any commands written during the Chip
Erase operation will be ignored.
Write Operation Status Detection
The SST39SF020 device provides two software means
to detect the completion of a Write (Program or Erase)
cycle, in order to optimize the system write cycle time.
The software detection includes two status bits : Data#
Polling (DQ7) and Toggle Bit (DQ6). The end of write
detection mode is enabled after the rising edge of WE#
which initiates the internal program or erase cycle.
The actual completion of the nonvolatile write is asyn-
chronous with the system; therefore, either a Data#
Polling or Toggle Bit read may be simultaneous with the
completion of the Write cycle. If this occurs, the system
may possibly get an erroneous result, i.e., valid data may
appear to conflict with either DQ7 or DQ6. In order to
prevent spurious rejection, if an erroneous result occurs,
the software routine should include a loop to read the
accessed location an additional two (2) times. If both
reads are valid, then the device has completed the Write
cycle, otherwise the rejection is valid.
Data# Polling (DQ7)
When the SST39SF020 device is in the internal Program
operation, any attempt to read DQ7 will produce the
complement of the true data. Once the Program opera-
tion is completed, DQ7 will produce true data. The device
is then ready for the next operation. During internal Erase
operation, any attempt to read DQ7 will produce a ‘0’.
Once the internal Erase operation is completed, DQ7 will
produce a ‘1’. The Data# Polling is valid after the rising
edge of fourth WE# (or CE#) pulse for Program opera-
tion. For sector or chip erase, the Data# Polling is valid
after the rising edge of sixth WE# (or CE#) pulse. See
Figure 6 for Data# Polling timing diagram and Figure 15
for a flowchart.


유사한 부품 번호 - SST39SF020-70-4C-W

제조업체부품명데이터시트상세설명
logo
Silicon Storage Technol...
SST39SF020A SST-SST39SF020A Datasheet
271Kb / 22P
   1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash
SST39SF020A SST-SST39SF020A Datasheet
379Kb / 24P
   1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash
logo
Microchip Technology
SST39SF020A MICROCHIP-SST39SF020A Datasheet
273Kb / 28P
   1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash
2013 04/13
SST39SF020A MICROCHIP-SST39SF020A Datasheet
227Kb / 29P
   1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash
04/16
SST39SF020A MICROCHIP-SST39SF020A Datasheet
3Mb / 29P
   1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash
2002-2016
More results

유사한 설명 - SST39SF020-70-4C-W

제조업체부품명데이터시트상세설명
logo
List of Unclassifed Man...
EN29F002N ETC-EN29F002N Datasheet
267Kb / 32P
   2 Megabit (256K x 8-bit) Flash Memory
logo
Eon Silicon Solution In...
EN29F002A EON-EN29F002A Datasheet
431Kb / 35P
   2 Megabit (256K x 8-bit) Flash Memory
logo
ATMEL Corporation
AT29C020 ATMEL-AT29C020 Datasheet
426Kb / 17P
   2-megabit (256K x 8) 5-volt Only Flash Memory
logo
Hynix Semiconductor
HY29F002T HYNIX-HY29F002T Datasheet
381Kb / 38P
   2 Megabit (256K x 8), 5 Volt-only, Flash Memory
logo
ATMEL Corporation
AT29LV020 ATMEL-AT29LV020_08 Datasheet
387Kb / 16P
   2-megabit (256K x 8) 3-volt Only Flash Memory
AT49F002 ATMEL-AT49F002 Datasheet
182Kb / 16P
   2-Megabit 256K x 8 5-volt Only Flash Memory
AT49F002 ATMEL-AT49F002 Datasheet
213Kb / 20P
   2-megabit (256K x 8) 5-volt Only Flash Memory
logo
Silicon Storage Technol...
SST39VF800Q SST-SST39VF800Q Datasheet
248Kb / 23P
   8 Megabit (512K x 16-Bit) Multi-Purpose Flash
logo
ATMEL Corporation
AT27C020 ATMEL-AT27C020_07 Datasheet
373Kb / 14P
   2-megabit (256K x 8) OTP EPROM
AT27C020 ATMEL-AT27C020 Datasheet
170Kb / 9P
   2-Megabit 256K x 8 OTP EPROM
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23


데이터시트 다운로드

Go To PDF Page


링크 URL




개인정보취급방침
ALLDATASHEET.CO.KR
ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com