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MC145200DT 데이터시트(PDF) 8 Page - Motorola, Inc |
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MC145200DT 데이터시트(HTML) 8 Page - Motorola, Inc |
8 / 23 page MC145200 •MC145201 MOTOROLA 8 PIN DESCRIPTIONS DIGITAL INTERFACE PINS Din Serial Data Input (Pin 19) The bit stream begins with the most significant bit (MSB) and is shifted in on the low–to–high transition of CLK. The bit pattern is 1 byte (8 bits) long to access the C or configuration register, 2 bytes (16 bits) to access the first buffer of the R register, or 3 bytes (24 bits) to access the A register (see Table 1). The values in the C, R, and A registers do not change during shifting because the transfer of data to the registers is controlled by ENB. CAUTION The value programmed for the N–counter must be greater than or equal to the value of the A–counter. The 13 least significant bits (LSBs) of the R register are double–buffered. As indicated above, data is latched into the first buffer on a 16–bit transfer. (The 3 MSBs are not double– buffered and have an immediate effect after a 16–bit trans- fer.) The second buffer of the R register contains the 13 bits for the R counter. This second buffer is loaded with the con- tents of the first buffer when the A register is loaded (a 24–bit transfer). This allows presenting new values to the R, A, and N counters simultaneously. If this is not required, then the 16–bit transfer may be followed by pulsing ENB low with no signal on the CLK pin. This is an alternate method of transferring data to the second buffer of the R register (see Figure 17). The bit stream needs neither address nor steering bits due to the innovative BitGrabber registers. Therefore, all bits in the stream are available to be data for the three registers. Random access of any register is provided. That is, the reg- isters may be accessed in any sequence. Data is retained in the registers over a supply range of 4.5 to 5.5 V. The formats are shown in Figures 15, 16, and 17. Din typically switches near 50% of VDD to maximize noise immunity. This input can be directly interfaced to CMOS de- vices with outputs guaranteed to switch near rail–to–rail. When interfacing to NMOS or TTL devices, either a level shifter (MC74HC14A, MC14504B) or pull–up resistor of 1 k Ω to 10 k Ω must be used. Parameters to consider when sizing the resistor are worst–case IOL of the driving device, maxi- mum tolerable power consumption, and maximum data rate. Table 1. Register Access (MSBs are shifted in first; C0, R0, and A0 are the LSBs) Number of Clocks Accessed Register Bit Nomenclature 8 16 24 Other Values ≤ 32 Values > 32 C Register R Register A Register See Figure 13 See Figures 22–25 C7, C6, C5, . . ., C0 R15, R14, R13, . . ., R0 A23, A22, A21, . . ., A0 CLK Serial Data Clock Input (Pin 18) Low–to–high transitions on CLK shift bits available at the Din pin, while high–to–low transitions shift bits from OUTPUT A (when configured as Data Out, see Pin 16). The 24–1/2–stage shift register is static, allowing clock rates down to dc in a continuous or intermittent mode. Eight clock cycles are required to access the C register. Sixteen clock cycles are needed for the first buffer of the R register. Twenty–four cycles are used to access the A regis- ter. See Table 1 and Figures 15, 16, and 17. The number of clocks required for cascaded devices is shown in Figures 24 through 26. CLK typically switches near 50% of VDD and has a Schmitt–triggered input buffer. Slow CLK rise and fall times are allowed. See the last paragraph of Din for more informa- tion. NOTE To guarantee proper operation of the power–on reset (POR) circuit, the CLK pin must be held at GND (with ENB being a don’t care) or ENB must be held at the potential of the V+ pin (with CLK be- ing a don’t care) during power–up. As an alterna- tive, the bit sequence of Figure 13 may be used. ENB Active Low Enable Input (Pin 17) This pin is used to activate the serial interface to allow the transfer of data to/from the device. When ENB is in an inac- tive high state, shifting is inhibited and the port is held in the initialized state. To transfer data to the device, ENB (which must start inactive high) is taken low, a serial transfer is made via Din and CLK, and ENB is taken back high. The low–to–high transition on ENB transfers data to the C or A registers and first buffer of the R register, depending on the data stream length per Table 1. NOTE Transitions on ENB must not be attempted while CLK is high. This puts the device out of synchro- nization with the microcontroller. Resynchroniza- tion occurs when ENB is high and CLK is low. This input is also Schmitt–triggered and switches near 50% of VDD, thereby minimizing the chance of loading erro- neous data into the registers. See the last paragraph of Din for more information. For POR information, see the note for the CLK pin. OUTPUT A Configurable Digital Output (Pin 16) OUTPUT A is selectable as fR, fV, Data Out, or Port. Bits A22 and A23 in the A register control the selection; see Figure 16. If A23 = A22 = high, OUTPUT A is configured as fR. This signal is the buffered output of the 13–stage R counter. The fR signal appears as normally low and pulses high, and can be used to verify the divide ratio of the R counter. This ratio extends from 5 to 8191 and is determined by the binary value loaded into bits R0 through R12 in the R register. Also, direct access to the phase detectors via the REFin pin is allowed by choosing a divide value of 1 (see Figure 17). The maximum frequency at which the phase detectors operate is 2 MHz. Therefore, the frequency of fR should not exceed 2 MHz. |
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