전자부품 데이터시트 검색엔진 |
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STK12C68-L25M 데이터시트(PDF) 3 Page - List of Unclassifed Manufacturers |
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STK12C68-L25M 데이터시트(HTML) 3 Page - List of Unclassifed Manufacturers |
3 / 13 page STK12C68 October 2003 3 Document Control # ML0008 rev 0.4 SRAM READ CYCLES #1 & #2 (VCC = 5.0V ± 10%)e Note g: W and HSB must be high during SRAM READ cycles. Note h: Device is continuously selected with E and G both low. Note i: Measured ± 200mV from steady state output voltage. SRAM READ CYCLE #1: Address Controlledg, h SRAM READ CYCLE #2: E Controlledg NO. SYMBOLS PARAMETER STK12C68-25 STK12C68-35 STK12C68-45 STK12C68-55 UNITS #1, #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX 1tELQV tACS Chip Enable Access Time 25 35 45 55 ns 2tAVAVg tRC Read Cycle Time 25 35 45 55 ns 3tAVQVh tAA Address Access Time 25 35 45 55 ns 4tGLQV tOE Output Enable to Data Valid 10 15 20 35 ns 5tAXQXh tOH Output Hold after Address Change 5 5 5 5 ns 6tELQX tLZ Chip Enable to Output Active 5 5 5 5 ns 7tEHQZi tHZ Chip Disable to Output Inactive 10 10 12 12 ns 8tGLQX tOLZ Output Enable to Output Active 0 0 0 0 ns 9tGHQZi tOHZ Output Disable to Output Inactive 10 10 12 12 ns 10 tELICCHf tPA Chip Enable to Power Active 0 0 0 0 ns 11 tEHICCLf tPS Chip Disable to Power Standby 25 35 45 55 ns DATA VALID 5 tAXQX 3 tAVQV DQ (DATA OUT) ADDRESS 2 tAVAV 6 tELQX STANDBY DATA VALID 8 tGLQX 4 tGLQV DQ (DATA OUT) E ADDRESS 2 tAVAV G ICC ACTIVE 1 tELQV 10 tELICCH 11 tEHICCL 7 tEHQZ 9 tGHQZ |
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