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ICS93732 데이터시트(Datasheet) 6 Page - Integrated Circuit Systems

부품명 ICS93732
상세내용  Low Cost DDR Phase Lock Loop Zero Delay Buffer
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제조사  ICST [Integrated Circuit Systems]
홈페이지  http://www.icst.com
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6
ICS93732
0578H—02/19/04
Bytes 0 to 4 are reseved power up default = 1. This allows operation with main clock.
Pin #
Name
0
1
PWD
Bit 7
2, 1
DDR0(T&C)
Output Control
RW
DISABLE ENABLE
1
Bit 6
4, 5
DDR1(T&C)
Output Control
RW
DISABLE ENABLE
1
Bit 5
-
-
Reserved
X
-
-
1
Bit 4
-
-
Reserved
X
-
-
1
Bit 3
13, 14
DDR2(T&C)
Output Control
RW
DISABLE ENABLE
1
Bit 2
17, 16
DDR3(T&C)
Output Control
RW
DISABLE ENABLE
1
Bit 1
-
-
Reserved
X
-
-
1
Bit 0
-
-
Reserved
X
-
-
1
Note:
Pin #
Name
0
1
PWD
Bit 7
-
-
Reserved
X
-
-
0
Bit 6
-
-
Reserved
X
-
-
0
Bit 5
-
-
Reserved
X
-
-
0
Bit 4
-
-
Reserved
X
-
-
1
Bit 3
24, 25
DDR4(T&C)
Output Control
RW
DISABLE ENABLE
1
Bit 2
-
-
Reserved
X
-
-
1
Bit 1
26, 27
DDR5(T&C)
Output Control
RW
DISABLE ENABLE
1
Bit 0
-
-
Reserved
X
-
-
1
Note:
Control Function
Affected Pin
BYTE
5
BYTE
6
PWD = Power Up Default
PWD = Power Up Default
Type
Bit Control
Type
Control Function
Affected Pin
Bit Control




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