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DAC1006LCWM 데이터시트(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
부품명 DAC1006LCWM
상세설명  uP Compatible, Double-Buffered D to A Converters
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제조업체  NSC [National Semiconductor (TI)]
홈페이지  http://www.national.com
Logo NSC - National Semiconductor (TI)

DAC1006LCWM 데이터시트(HTML) 3 Page - National Semiconductor (TI)

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Electrical Characteristics
Tested at VCC e 475 VDC and 1575 VDC TAe25 C VREFe10000 VDC unless otherwise noted (Continued)
See
VCCe12VDCg5%
VCCe5VDCg5%
Parameter
Conditions
Note
to 15VDCg5%
Units
Min
Typ
Max
Min
Typ
Max
Output Leakage
TMINsTAsTMAX
6
Current
IOUT1
All data inputs
latched low
10
200
200
nA
IOUT2
All data inputs
latched high
200
200
nA
Digital Input
TMINsTAsTMAX
6
Voltages
Low level
LCN and LCWM suffix
08 08
07 08
VDC
High level (all parts)
20
20
VDC
Digital Input
TMINsTAsTMAX
6
Currents
Digital inputs k08V
b
40
b
150
b
40
b
150
m
ADC
Digital inputs l20V
10
a
10
10
a
10
m
ADC
Current Settling
tS
VILe0V VIHe5V
500
500
ns
Time
Write and XFER
tW
VILe0V VIHe5V
Pulse Width
TAe25 C
8
150
60
320
200
ns
TMINsTAsTMAX
9
320
100
500
250
ns
Data Set Up Time
tDS
VILe0V VIHe5V
TAe25 C
9
150
80
320
170
ns
TMINsTAsTMAX
320
120
500
250
ns
Data Hold Time
tDH
VILeOV VIHe5V
TAe25 C
9
200
100
320
220
ns
TMINsTAsTMAX
250
120
500
320
ns
Control Set Up
tCS
VILe0V VILe5V
Time
TAe25 C
9
150
60
320
180
ns
TMINsTAsTMAX
320
100
500
260
ns
Control Hold Time
tCH
VILe0V VIHe5V
TAe25 C
9
10
0
10
0
ns
TMINsTAsTMAX
10
0
10
0
ns
Note 1
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions
Note 2
All voltages are measured with respect to GND unless otherwise specified
Note 3
This 500 mW specification applies for all packages The low intrinsic power dissipation of this part (and the fact that there is no way to significantly modify
the power dissipation) removes concern for heat sinking
Note 4
For current switching applications both IOUT1 and IOUT2 must go to ground or the ‘‘Virtual Ground’’ of an operational amplifier The linearity error is
degraded by approximately VOSdVREF For example if VREFe10V thena1mV offset VOS onIOUT1 or IOUT2 will introduce an additional 001% linearity error
Note 5
Guaranteed at VREFeg10 VDC and VREFeg1VDC
Note 6
TMINe0 C and TMAXe70 C for ‘‘LCN’’ and ‘‘LCWM’’ suffix parts
Note 7
The unit ‘‘FSR’’ stands for ‘‘Full Scale Range’’ ‘‘Linearity Error’’ and ‘‘Power Supply Rejection’’ specs are based on this unit to eliminate dependence on a
particular VREF value and to indicate the true performance of the part The ‘‘Linearity Error’’ specification of the DAC1006 is ‘‘005% of FSR (MAX)’’ This
guarantees that after performing a zero and full scale adjustment (See Sections 25 and 26) the plot of the 1024 analog voltage outputs will each be within
005%cVREF of a straight line which passes through zero and full scale
Note 8
This specification implies that all parts are guaranteed to operate with a write pulse or transfer pulse width (tW) of 320 ns A typical part will operate with tW
of only 100 ns The entire write pulse must occur within the valid data interval for the specified tW tDS tDH and tS to apply
Note 9
Guaranteed by design but not tested
Note 10
A 200 nA leakage current with Rfbe20K and VREFe10V corresponds to a zero error of (200c10b9c20c103)c100d10 which is 004% of FS
Note 11
Human body model 100 pF discharged through a 15 kX resistor
3


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