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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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54LS256FMQB 데이터시트(PDF) 1 Page - National Semiconductor (TI) |
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54LS256FMQB 데이터시트(HTML) 1 Page - National Semiconductor (TI) |
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1 / 6 page  TLF9823 June 1989 54LS256DM74LS256 Dual 4-Bit Addressable Latch General Description The ’LS256 is a dual 4-bit addressable latch with common control inputs these include two Address inputs (A0 A1) an active LOW enable input (E) and an active LOW Clear input (CL) Each latch has a Data input (D) and four outputs (Q0 – Q3) When the Enable (E) is HIGH and the Clear input (CL)is LOW all outputs (Q0 – Q3) are LOW Dual 4-channel demul- tiplexing occurs when the CL and E are both LOW When CL is HIGH and E is LOW the selected output (Q0 – Q3) determined by the Address inputs follows D When the E goes HIGH the contents of the latch are stored When op- erating in the addressable latch mode (E e LOW CL e HIGH) changing more than one bit of the Address (A0 A1) could impose a transient wrong address Therefore this should be done only while in the memory mode (E e CL e HIGH) Features Y Serial-to-parallel capability Y Output from each storage bit available Y Random (addressable) data entry Y Easily expandable Y Active low common clear Connection Diagram Dual-In-Line Package TLF9823 – 1 Order Number 54LS256DMQB 54LS256FMQB or DM74LS256N See NS Package Number J16A N16E or W16A Logic Symbol TLF9823 – 2 VCC e Pin 16 GND e Pin 8 Pin Names Description A0 A1 Common Address Inputs Da Db Data Inputs E Common Enable Input (Active LOW) CL Conditional Clear Input (Active LOW) Q0a–Q3a Side A Latch Outputs Q0b–Q3b Side B Latch Outputs C1995 National Semiconductor Corporation RRD-B30M115Printed in U S A |
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유사한 설명 - 54LS256FMQB |
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